[SI-LIST] Re: Noise in PCB vias
- From: Vadim Heyfitch <htc2rl@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 20 Nov 2003 12:14:59 -0800 (PST)
Bonjour, JP -
the least you can and should do is make sure the via
pad stack is balanced. The via inductance number taken
by itself is meaningless. It should be "balanced out"
by the via capacitance so that the via's impedance is
as close as possible to that of the trace. This is
accomplished by adjusting via and anti-pad sizes. If
the anti-pad is too large, compared to the via barrel
diameter then the via is going to be more inductive
than capacitive. (TDR will show an upward blip) If the
gap is two small then the via capacitance will
dominate (the downward blip on TDR)
Good luck.
-Vadim Heyfitch
--- Jean_Pierre.Bouthemy@xxxxxxxxxx wrote:
> Hi SI experts,
>
> I have an issue with noise in vias on our V2Pro FPGA
> to QDRII interface.
> The clock frequency is 125MHz.
> My question is thus the following:
> Do you know any reltionship between a PCB via
> finished hole diameter and
> maximum current or maximum frequency through it?
> Is there any formula, table?
> For your information, our via diameter (finished
> hole) is around 8 mils
> with total board thickness is 110 mils.
> The calculated via inductance (with Istan Novak's
> excel spreadsheet) gives
> Lvia = 2nH.
>
> Thank you for your help.
> Regards.
>
> JP
>
--------------------------------------------------------------------------
> Jean-Pierre BOUTHEMY
> Hardware Design Engineer
> ALCATEL - Mobile Networking Division (MCG)
> Mobile Core R&D
> +33 (0)2 99 26 08 18
> mailto:jean_pierre.bouthemy@xxxxxxxxxx
>
>
>
>
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