[SI-LIST] Noise in PCB vias
- From: Jean_Pierre.Bouthemy@xxxxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 20 Nov 2003 18:10:07 +0100
Hi SI experts,
I have an issue with noise in vias on our V2Pro FPGA to QDRII interface.
The clock frequency is 125MHz.
My question is thus the following:
Do you know any reltionship between a PCB via finished hole diameter and
maximum current or maximum frequency through it?
Is there any formula, table?
For your information, our via diameter (finished hole) is around 8 mils
with total board thickness is 110 mils.
The calculated via inductance (with Istan Novak's excel spreadsheet) gives
Lvia = 2nH.
Thank you for your help.
Regards.
JP
--------------------------------------------------------------------------
Jean-Pierre BOUTHEMY
Hardware Design Engineer
ALCATEL - Mobile Networking Division (MCG)
Mobile Core R&D
+33 (0)2 99 26 08 18
mailto:jean_pierre.bouthemy@xxxxxxxxxx
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