Rules of thumb work best in butcher shops where the butcher puts his thumb on
the scale when you are not looking. As Eric Bogatin would tell you, they are
useful to see if you are headed in the right direction, but the task needs to
be done with proper analysis and measurement to make sure the design is done
right. Yes, that is a lot of hard, tedious engineering, but so is the
engineering required to build a successful suspension bridge!
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Cosmin Iorga (Redacted sender "ci42775" for DMARC)
Sent: Friday, November 4, 2016 1:27 PM
To: jonathan@xxxxxxx; asparky@xxxxxxxxxxxxxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Noise coupling between parallel power planes
From my experience, rules of thumb are a good start but they don't fit all
specific cases. In my work so far all power integrity analysis and issues
always narrowed-down to fundamental concepts: understanding from where to where
the transient currents flow and what is the loop inductance of those paths.
Since I understand that your application is on an FPGA, you may find
interesting a technique that I have developed and published in two papers at
DesignCon2012 that cover decupling capacitors optimization and debugging power
integrity issues in FPGA applications. You can download the two papers from my
website http://www.noisecoupling.com ;(under the tab "Power Integrity
Solutions"). Also feel free to contact me .
Best Wishes,
Cosmin
--------------------------------------------
On Fri, 11/4/16, Aubrey Sparkman <asparky@xxxxxxxxxxxxxxxxxxxxxxxx> wrote:
Subject: [SI-LIST] Re: Noise coupling between parallel power planes
To: jonathan@xxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Date: Friday, November 4, 2016, 8:07 AM
One solution is to use a
PWR-GND-PWR-GND configuration instead. Then put Low speed (i2c and JTAG,
etc) and static signals on the signal layer next to the power plane. This
configuration allows you to minimize thickness. The FPGA core might be a
good choice for that top pwr plane, it isn't going to be all that noisy
compared to the 12V, 5V, 3.3V rails.
Aubrey
Sent from my iPhone
On Nov 4, 2016, at 9:26 AM, JonathanSalkind <jonathan@xxxxxxx>
experts,
Hi
anyone done analysis on noise coupling between parallel power planes? > >
Has
https://www.freelists.org/post/si-list/Power-plane-coupling,7"One way to decrease the vertical coupling is to increase > the relative
Dr. Novak writes,
Searching online, I found this whitepaper, but it didn't really get into >
https://www.cst.com/Content/Articles/article874/CST-Whitepaper-Analyzing-Power-Integrity-Issues-Power-Plane-Interaction.pdf
In a multi-layer board, I often need a four-plane-layer > stack of
More specifically:
where I have a FPGA core rail (maybe ~20A and fairly
One use case is
on one of the power layers, andFPGA 10Gb transceiver rails on the adjacent > power layer. The transceiver
have good rules of thumb for the ratio between PWR-PWR and > PWR-GND in
Does anyone
Does anyone know of any other PDFs or articles online which analyze this >Shlepnev, would you consider doing a SIMBEOR demo video evaluating >
situation?
Dr.
Thanks,
Jon------------------------------------------------------------------
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