From my experience, rules of thumb are a good start but they don't fit all
specific cases. In my work so far all power integrity analysis and issues
always narrowed-down to fundamental concepts: understanding from where to where
the transient currents flow and what is the loop inductance of those paths.
Since I understand that your application is on an FPGA, you may find
interesting a technique that I have developed and published in two papers at
DesignCon2012 that cover decupling capacitors optimization and debugging power
integrity issues in FPGA applications. You can download the two papers from my
website http://www.noisecoupling.com ;(under the tab "Power Integrity
Solutions"). Also feel free to contact me .
Best Wishes,
Cosmin
--------------------------------------------
On Fri, 11/4/16, Aubrey Sparkman <asparky@xxxxxxxxxxxxxxxxxxxxxxxx> wrote:
Subject: [SI-LIST] Re: Noise coupling between parallel power planes
To: jonathan@xxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Date: Friday, November 4, 2016, 8:07 AM
One solution is to use a
PWR-GND-PWR-GND configuration instead. Then put
Low speed (i2c and JTAG, etc) and static signals on the
signal layer next to the power plane. This configuration
allows you to minimize thickness. The FPGA core might be a
good choice for that top pwr plane, it isn't going to be
all that noisy compared to the 12V, 5V, 3.3V rails.
Aubrey
Sent from my iPhone
On Nov 4, 2016, at 9:26 AM, JonathanSalkind <jonathan@xxxxxxx>
experts,
Hi
anyone done analysis on noise coupling between parallel
Has
Searching the SI-List archives, I found this note from
points out the needto consider the issue:
https://www.freelists.org/post/si-list/Power-plane-coupling,7"One way to decrease the vertical coupling is to
Dr. Novak writes,
the relative separationbetween the two power planes. This can be done by
either increasing the absolute separationvertically between the two power
planes, or reducing the separation between the power planes
planes, or a combination ofboth." I already practice this when possible,
but there are times when some coupling isunavoidable.
Searching online, I found this whitepaper, but it didn't
practical designaspects, or variation of plane separation:
https://www.cst.com/Content/Articles/article874/CST-Whitepaper-Analyzing-Power-Integrity-Issues-Power-Plane-Interaction.pdf
In a multi-layer board, I often need a four-plane-layer
More specifically:
stack of GND-PWR-PWR-GND somewhere, using1oz copper. Obviously I want the
PWR-PWR dielectric separation to be greater than the GND-PWR
but how much greater? MyPCBs are often limited in thickness due to
mechanical constraints, so separationgreater than 4 or 5 mils (or complete
GND-PWR-GND isolation) is very challenging or completely
achieve.where I have a FPGA core rail (maybe ~20A and fairly
One use case is
on one of the power layers, andFPGA 10Gb transceiver rails on the adjacent
power layer. The transceiver rails aredesigned and analyzed and
appropriatelybypassed to meet the stringent specifications of the FPGA
manufacturer, but my analysis considersthat rail and its copper in
isolation,not factoring in coupling from an adjacent plane. I know
"fairly noisy" is notactually a meaningful phrase, but I'm wondering if
some of the experts on the forum havealready analyzed situations similar to
this.
have good rules of thumb for the ratio between PWR-PWR
Does anyone
PWR-GND in these situations? Forexample, if there is a 4 mil dielectric
PWR-PWR, is a 2 mil dielectric sufficient for PWR-GND, or is
to go to 1 mildielectric (e.g. FaradFlex or Interra) PWR-GND in order
reduce the PWR-PWR coupling? Iknow rules of thumb are blunt instruments,
but as Dr. Bogatin's Rule of Thumb #0says, "an ok answer NOW! is better
than a good answer, late."
Does anyone know of any other PDFs orarticles online which analyze this
situation?
Shlepnev, would you consider doing a SIMBEOR demo video
Dr.
parallel plane interactionsbetween power layers in a GND-PWR-PWR-GND
four-layer stackup? Your educationalvideo series this year has been quite
informative.
Thanks,
Jon------------------------------------------------------------------
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