[SI-LIST] Net seminar on designing high speed channels
- From: "Leonard Dieguez" <ldieguez@xxxxxxxxxx>
- To: "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 9 Jul 2007 09:37:52 -0700
http://www.altera.com/education/net_seminars/all/ns-gigabit-interconnect
.html
above is a link to the net seminar that I recorded. It was just
released.
http://tinyurl.com/ypzsf3
(tiny URL version)
I'm sure that some of you will find it amusing and some of you will find
some room for improvement. Feel free to email me suggestions on how I
can improve this for future presentations.
Below is the subject matter.
Leonard Dieguez
ldieguez@xxxxxxxxxx
Overview
Though high-speed serial links increase data throughput and reduce the
number of traces on a board, a different set of challenges arise when
designing these systems. This seminar provides useful guidelines and
techniques when designing a high-speed channel. The seminar will cover a
channel model case study that includes how to address the challenges of
designing at high data rates (BGA breakout, crosstalk, vias, DC block
capacitor, and an SMA connector). These challenges are tied in and are
implemented in a complete end-to-end channel simulation.
At this net seminar, you'll learn how to:
Address high-speed channel design challenges
Analyze modeled and simulated high-speed interconnects
Employ a simulation environment for an end-to-end channel
Who Should View
System architects
Hardware and system design engineers
FPGA developers
Signal integrity engineers
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