[SI-LIST] Re: Need help on TDR sim
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 23 Dec 2013 05:52:15 -0800
These sorts of symptoms can occur with short low loss lines.
Steve
On 12/23/2013 5:04 AM, Sureshkumar Ayyavu wrote:
> Hi Guys ,
> Anybody help me to understand the TDR plot. While doing my HSPICE
> simulation , I see the inductive and capacitive peaks continuously. Guys
> please let me know if we have any defined way to determine the peaks
> location in my PCB trace.
>
> Is it correct , if we use the propagation delay of the trace to find out
> the TDR peaks location. It is not working in my case. My stripline is
> pretty clear. It is connected bt the BGA and SMA. I used the models for BGA
> and SMA. And did the seperate TDR simulation for these models too. It works
> good. So i conclude the issue is in the board touchstone file.
>
> THANKS
> Suresh
>
>
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