[SI-LIST] Re: Need for parallell termination to Vtt on DDR SDRAM?
- From: Dan Bostan <dbostan@xxxxxxxxx>
- To: svein.medhus@xxxxxxx, si-list <si-list@xxxxxxxxxxxxx>
- Date: Thu, 9 Jun 2005 14:22:41 -0700 (PDT)
It can be done, but the topology must be simulated for
SI.
/dan
--- Svein Medhus <svein.medhus@xxxxxxx> wrote:
> Dear List,
> We are making an embedded design using Freescale
> MPC5200 with DDR-memory. Does anyone have experience
> with this?
>
> We are planning to use series terminations on all
> signals, and a resistor divider ( with capacitor to
> GND) for the Vref voltage on the DDR. Clock speed is
> 133MHz. There is only one bank of DDR-memory
> connected to the MPC5200. Basically a point to point
> connection. We have done several designs with other
> Freescale processors, but then with SDR-SDRAM
>
> Is there in this simple case any reason for making
> parallel termination at the end of each signal to
> Vtt?
>
> Any other known issues to look out for on DDR
> compared to SDR-memories, particular with the
> MPC5200?
>
> Some feedback will be much appreciated.
>
> Svein Medhus
> ITec Consulting AS
>
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