[SI-LIST] Re: Need advice on basic 6-layer stackup
- From: "lgreen" <lgreen22@xxxxxxxxxxxxxx>
- To: <GrahamDavies@xxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Sat, 16 Apr 2005 09:06:56 -0700
Hello, Graham,
There are any number of PCB prototypes that failed on "slow" nets due to SI
problems. It is the IC edge rate, rather than the clocking, that can cause
crosstalk and to overvoltage stress on unterminated receivers.
These days, the silicon designers push for speed, and PCB designers get to
deal with the consequences. Sigh...
- Lynne
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Graham Davies
Sent: Saturday, April 16, 2005 7:37 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Need advice on basic 6-layer stackup
I have joined a small company that has no established experience in
signal integrity. I have inherited a product that has a lot of
problems that I believe are due to lousy signal integrity. I am
looking for guidance in selecting a good basic stackup for a redesign
of the PCB. I have spent a lot of time Googling for this and ended up
here.
The current PCB is 6 layer as follows: component side signals, ground
plane, inner signals, power plane, ground plane, bottom side signals.
Minimum trace width and spacing are both 0.006 in. Material is 1/16
inch FR4 with 1 oz finished copper thickness for all layers. Maximum
signal frequency is, I think, 40 MHz and there's really nothing very
special going on anywhere. It's all pretty low tech and the design is
five years old.
I have two revisions of the board. Both have the basic layer order as
above but completely different layer separations. I think the layer
order is fine, but I'm not really happy with either set of separations
so this is where I'm asking for help.
The first revision has 0.008 in. between the outer signal layers and
the ground planes. Inside this is a 0.0145 in. separation. Then the
inner signal layer is referenced to the power plane and has a 0.007 in.
spacing from it. The type of problem this board has is that it will
run for a while and then crash. I think there is serious crosstalk as
traces are closer to their neighbors on the same layer than to their
reference planes. Also, the power plane has no really close ground
plane to form a distrubuted decoupling capacitor.
The second revision has 0.0032 in. between the outer signal layers and
the ground planes. Inside this is a 0.004 in. separation. The inner
signal layer is therefore referenced to a ground plane. The power
plane is not used as a reference and is very close to the other ground
plane. The board thickness is made up with 0.038 in. in the middle. I
have found only one problem with this board so far which is consistent
though temperature dependent and can be fixed with a series resistor at
the driving point of a badly routed clock trace. It slows the edge so
as to increase the overlap of the outgoing and reflected signal edges.
So, anyway, the second board with 3.2 : 4 : 38 : 4 : 3.2 mil
separations is clearly the better of the two, but for such a low tech
board the trace impedance seems rather low (40 ohms?). If I go with
this I think I'll need to add high-strength drivers all over. I'm
wondering if something like 5 : 7 : 28 : 7 : 5 wouldn't be a better
choice with an impedance of around 58 ohms? Or 4 : 6 : 32 : 6 : 4 for
around 50 ohms? Can someone help me out here? I can't figure out how
my choice of separations affects the manufacturability of the PCB
either. Google has never before let me down so badly.
Graham.
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