In my case (FPGA), every pin delay is different. It depends on the place and
route of the core. So I must take into consideration pin delay as part of total
delay in order to match lenght.
I am not sure if I have understood your post.
Kindly
Ivan Perino
On 14/08/2015, at 10:24, "Kishorekumar Mohandas" <kishorekumar.moh@xxxxxxx>------------------------------------------------------------------
wrote:
Hi All,
We're using Cadence PCB Designer for our Layout design. Wherever we're doing
length matching we're considering the Pin delay information of controller
(Driver). My question is that, as all the timing parameters are defined at
the pin what is the necessity of considering pin delay for length matching.
Kindly share your opinions.
Regards,
Kishore Kumar
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