[SI-LIST] Re: My way to Kill ripple noise on the power rail
- From: "Ray Anderson" <ray.anderson@xxxxxxxxxx>
- To: <Charles.Grasso@xxxxxxxxxxxx>, <heinrich.smith2005@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 12 Jul 2007 09:56:10 -0700
Charles-
For measuring low impedances such as found in PDNs, S21 measurements are
much more effective than S11 measurements. Using S11 it is difficult to
measure very low Z accurately due to probing parasitics (L primarily).
See some of the papers on the topic written a few years back by Istvan
Novak and also Larry Smith and myself.
Regards,
-Ray
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Grasso, Charles
Sent: Thursday, July 12, 2007 9:13 AM
To: heinrich.smith2005@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: My way to Kill ripple noise on the power rail
Nice analysis.
I suppose the trick is step3. Using a VNA can be tricky when
measuring a low impedance plane. Also typically folks measure
S11 not S21. Typically how do you choose the two measurement points?
Best Regards
Charles Grasso
Compliance Engineer
Echostar Communications Corp.
Tel: 303-706-5467
Fax: 303-799-6222
Cell: 303-204-2974
Pager/Short Message: 3032042974@xxxxxxxxx
Email: charles.grasso@xxxxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Heinrich.Smith
Sent: Thursday, July 12, 2007 8:22 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] My way to Kill ripple noise on the power rail
About one years ago, i had ripple noise problem when the specific test
program was enable.
I fixed it by measurement and simulation.
My way to Kill ripple noise on the power rail shows as below:
step 1:
measure the ripple voltage by the scope at the specific test condition.
the test condiction could be normal operation of the system or running
stress program or stimulate 101010 on each bit to busy the bus
traffic...
Anyway,
The first job is to capture the biggest ripple voltage that you are
suffering .I assume it as delta-v
(I am used to investigate the waveform from ms->us->ns by tunning time
scale)
step 2:
To see the repeated period on time scale and judge the ripple is
contributed
mostly by x MHz.
step 3:
To Get power rail's Z-profile by VNA(S21->Z21),pick up the Z value at x
MHz.I assume its value is z.
So i get an estimate delta current at x MHz, i=3D3D delta-v/z
step 4:
If i want to reduce delta-v to delta-v",i define a Z_target as
delta-v"/i ,
"i" is gotten by step 3.
step 5:
You can use the Z_target(gotten from step 4) as our goal to reduce
ripple
voltage at x MHZ and set this criteria on your PI simulation tool like
Cadence SQ-PI,Sigrity PowerSI,or Ansoft SI-Wave.
step 6:
After the simulation work of step 5, you should get the decap strategy
include value,number, and placement.(note,it is effective only around x
MHz).
then,
re-work your board and measure ripple noise again.
After you successfully kill the ripple voltage at x MHz, you will more
likely to see the secondary ripple voltage.
The same, follow the above procedure to kill it again till the overall
ripple noise is under the spec.
That's my experience for you reference.
Any comments and possible improvement are welcome to share with me.
Thank you!
-Heinrich
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