[SI-LIST] Re: Multiple series caps in signal lines
- From: steve weir <weirsi@xxxxxxxxxx>
- To: "Bowden, Ivor" <ibowden@xxxxxxxxxxxxxxxxx>
- Date: Wed, 23 Jul 2008 13:09:30 -0700
Ivor, depending on their exposure, it is possible for the lines in the=20
middle to acquire an induced charge from ESD, EFT, to a lesser extent=20
hot plugs etc. If the lines are striplines ESD, EFT exposure is low,=20
and the small leakage through the PCB s/b enough to drain off any energy =
that gets stored. If you are really worried about this, you could place =
high value resistors in parallel with one set of the caps, preferably=20
the receiver. The high value resistors will simply end-up biasing the=20
otherwise floating nodes at the nominal receiver bias. The alternative=20
is to use a resistor to ground on each line. I have not seen this done=20
in backplanes. It could make sense where the Tx media is long and=20
exposed to the outside world, like in cabinet to cabinet applications. =20
Other alternatives are to use higher voltage rated capacitors,=20
transformer isolation, or move to FO.
Best Regards,
Steve.
Bowden, Ivor wrote:
> Hi SI experts,
> =20
>
> Consider a hypothetical case where a serial line has a series cap at th=
e TX and also the RX. The center segment of the signal line would be floa=
ting in a DC sense. Say the physical implementation of the center section=
could be PCB trace, wire, coax, etc.
>
> =20
>
> What types of problems, if any, should one expect with this arrangement=
?
>
> =20
>
> Thanks,
>
> =20
>
> Ivor Bowden
>
> Senior Hardware Engineer
>
> Curtiss-Wright Controls Embedded Computing
>
> 10201 Wateridge Circle
>
> Suite 300
>
> San Diego, CA 92121
>
> 858-452-0020 x 4405
>
> ibowden@xxxxxxxxxxxxxxxxx
>
> =20
>
>
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--=20
Steve Weir
Teraspeed Consulting Group LLC=20
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