No, the Xilinx LUT is an SRAM based look-up table. It is part of a configurable logic block that contains registers and multiplexors in addition to LUTs. The Actel logic block is based on a 4 input mux. If Amr Moshen were not cooling his heels in federal prison, he could explain his architecture. Steve. On 9/19/2014 5:30 AM, Chauhan, Rajat wrote: > Yes, Xilinx LUT is programmable registers followed by MUX (or layer of MUXs) > > -----Original Message----- > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On > Behalf Of Hal Murray > Sent: Friday, September 19, 2014 1:01 PM > To: si-list@xxxxxxxxxxxxx > Cc: Hal Murray > Subject: [SI-LIST] Re: Multi Billion Dollar Company That Uses Only > Multiplexers > >> No, Xilinx is based on LUT's. > One way to build a LUT is with a pyramid of muxes, one layer for each address > bit. > > > > -- Steve Weir IPBLOX, LLC 1580 Grand Point Way MS 34689 Reno, NV 89523-9998 www.ipblox.com (775) 299-4236 Business (866) 675-4630 Toll-free (707) 780-1951 Fax All contents Copyright (c)2013 IPBLOX, LLC. All Rights Reserved. This e-mail may contain confidential material. If you are not the intended recipient, please destroy all records and notify the sender. ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List forum is accessible at: http://tech.groups.yahoo.com/group/si-list List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu