[SI-LIST] Re: Modeling Metal Traces On-chip

  • From: Vadim Heyfitch <htc2rl@xxxxxxxxx>
  • To: pzilaro@xxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Sun, 11 Jan 2004 17:31:55 -0800 (PST)

Patrick,

where (in a flip-chip BGA) bumps of the silicon
interface to the package - there is no real reference
plane. Same is true for the RDL (the top metal layers 
on Si). The return currents flow - mainly but not
exclusively - in the nearest "fat" PWR and/or GND
metal traces of the IO group of s/p/g buffers. Since
on RDL there are many signals between any nearest
PWR/GND "fat" traces, all those signal currents share
the same return paths. It is a really 3D, rather messy
problem, which is, as they say, "an area of active
research". Some tools model (or "extract") equivalent
ckts for RDL by making some, very crude assumptions.
One example of such assumptions would be the one that
the nearest PWR or GND trace on a redistribution layer
serves as a return path - not any other close-up
signal trace, not the second nearest PWR/GND trace
(which is considered to be the shadow of the nearest
one). Although commercial silicon tools cost many
$100k, their level of sophistication - when it comes
to the nitty-gritty algorithms - is limited by what
can be found in, bought or licensed from academia. 

-Vadim

--- Patrick Zilaro <pzilaro@xxxxxxxxxxxx> wrote:
> Dear SI Experts,
> 
> I have a question regarding modeling signal traces
> on the IC.  When is it
> correct to consider the silicon substrate as a
> reference (i.e. return path)
> for these signals?  If you reference the traces to
> the package GND, then the
> inductance is obviously much higher than referencing
> them to the silicon
> substrate.  An example of this would be RDL
> (re-distribution layer) traces
> for flip-chip designs.
> 
> Would semiconductor device physics software be
> required to accurately model
> this?  Your opinions are welcome.
> 
> 
> Regards,
> 
> Patrick Zilaro, SI Packaging Engineer
> Broadcom Corporation
> 
> 
>
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