[SI-LIST] Minimize SSN and Jitter with Advanced Transceiver Technology

From: Salman Jiva <sjiva@xxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Wed, 4 Jun 2008 09:44:44 -0700

Enjoy!
 
As data rates and the number of transceiver channels in advanced FPGAs
increase, it's increasingly important that the FPGA is designed to
properly isolate analog and digital sources. This webcast presents
available architectural advantages, and describes how those advantages
minimize the effects of simultaneous switching noise (SSN) and jitter.
 
http://www.accelacomm.com/jlp/si_list/0/80405710/
Available Now, On-Demand
Length: 30 minutes
 
Presenter: Dr. Mike Peng Li
Principal Architect and Distinguished Engineer, Altera Corporation
 
 
Salman Jiva
Altera Corporation
 

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[SI-LIST] Minimize SSN and Jitter with Advanced Transceiver Technology

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