[SI-LIST] Re: Metal Fills?

  • From: <Christopher.Jakubiec@xxxxxxxxxxxx>
  • To: <khemani_manish@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 6 May 2005 17:10:32 -0700

Hi Manish,

Metal fill is a technique that is used generally in copper metal layer
processes to aid the CMP (chemical mechanical polishing) step.
Essentially metal is used to fill in the gaps between the circuitry in
the die, and in turn this extra metal causes additional parasitic
capacitance.

When I used to perform wafer level technology characterization we used
to place devices on test wafers with and without metal fill, and the
difference in capacitance can be significant.

-Chris
Infineon Technologies


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of manish khemani
Sent: Friday, May 06, 2005 6:26 PM
To: SI-list
Subject: [SI-LIST] Metal Fills?


Hi,

What exactly are metal fills? I have read that they
affect parasitic capacitance which in turn affect
delay calculation and crosstalk calculation. But I am
not able to understand why? your help will be greatly appreciated.

Thanks and regards,
Manish Khemani.
Graduate student
CSUN


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