[SI-LIST] Re: Memory bus datapattern
- From: "David Banas" <david.banas@xxxxxxxxxx>
- To: <homer.si.mpson66@xxxxxxxxx>
- Date: Tue, 24 Apr 2007 13:15:44 -0700
Peter,
If the coupling between package nets is predominantly inductive, which
it usually is, and if the inductive coupling effect overwhelms any
internal power rail droop or ground bounce effects on signal timing,
then setting a "victim" to toggle out of phase with the remaining 31
"aggressors" (all toggling in phase with each other) will give a good
estimate of worst case "push-in" (i.e. - edge advance) on the victim,
while toggling it in phase with those aggressors gives a good estimate
of worst case "push-out" (i.e. - edge retard).
With regard to internal power rail droop and ground bounce, I would
think that toggling all 32 lines in phase with each other would give the
worst case results.
-db
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Peter Johansson
> Sent: Tuesday, April 24, 2007 8:52 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Memory bus datapattern
>=20
> Hi everybody,
> I have a problem with how to define a reasonable worst case
datapattern on
> a
> DDR data bus to calculate crosstalk and SSN on the power supply.
>=20
> Should I assume that all 32 bits start in a low/high state and change
> simultaneously or is there a better choice?
> I mean, all bits will not change at the same time, which means that I
will
> design towards a worst worst case instead of a real worst case.
> Have someone made some statistical analysis of how many bits are
high/low
> and how many will change state every cycle?
>=20
> Any ideas?
>=20
> BR
> Peter
>=20
> PS I'm a Homer fan if someone wonders
>=20
>=20
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>=20
>=20
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