Hi Robert, I agree - the subject of analysis of via-holes is not so simple as it seems. Validation with the measurements is also difficult, especially for well-designed vias or launches due to relatively small reflections, manufacturing tolerances, unknown material properties, fuzzy models and measurements and so on. First of all, you have to separate vias that can be simulated in isolation (localizable) from the vias dependent on the board geometry (non-localizable). I wrote about it multiple time - apologize for the repeat. Examples of localizable vias are single-ended vias with sufficient number of electrically close stitching vias. The number of stitching vias and distance to signal via define the upper localization frequency. Differential vias can be simulated in isolation for differential mode only if no stitching vias. Differential vias with stitching vias are conditionally localizable for both modes. Analysis of non-localizable vias depends on the board geometry as it says, not possible in pre-layout stage and either extremely time-consuming or simply not possible in post-layout stage with accuracy sufficient for 10G channels (20 GHz upper frequency). Analysis of non-localizable vias in isolation produce results dependent on multiple factors such as simulation area size and boundary conditions and thus not usable. Let's assume you have vias that can be simulated in isolation up to your target frequency (20 GHz). The analysis of a localizable vias in different 3D electromagnetic tool should produce reasonably close results (exact match is typically not possible due to differences in algorithms). If 2 tools produced considerably different results, try to increase the accuracy in both and see if the results converge. If not, get a third tool to validate the results. Tools without 3D EM via models is not a reliable option for your target frequency range. Considering the validation with measurements, one via with two line segments or two vias separated with a line segment are preferable structures to my opinion. In any case you have to design and validate the launches first. Pads for micro-probes is probably the easiest to design. Another option is to use a coaxial connector - the launches in this case are also vias and the model may need validation. Line segments with 2 launches can be used to validate the launch and also re-used to extract the material parameters. Alternatively, TRL de-embedding can be used to eliminate the effect of the launches from the measured S-parameters (though it is relatively difficult on a cheap FR4-type laminate). As I noted before, the material parameters identification must be pre-requisite in any validation project. It can be done with GMS-parameters for instance - I will talk about it at the webinar tomorrow http://www.simberian.com/Webinars.php. Note, that some simple boards with thick internal dielectric layers may require anisotropic dielectric model for via analysis - XY components of Dk may be up to 10-20% larger comparing to Z-component (due to multi-layered structure of laminate). Best regards, Yuriy Yuriy Shlepnev, Ph.D. President, Simberian Inc. 3030 S Torrey Pines Dr. Las Vegas, NV 89146, USA Office +1-702-876-2882 Cell +1-206-409-2368 Skype: shlepnev www.simberian.com -----Original Message----- From: Robert Haller [mailto:rhaller@xxxxxxxxxxxxx] Sent: Monday, June 11, 2012 8:30 AM To: shlepnev@xxxxxxxxxxxxx; Ravinder.Ajmani@xxxxxxxx; si-list@xxxxxxxxxxxxx Subject: RE: [SI-LIST] Re: Measurement/Simulation Correlation I have what I think is a pretty simple question that may not be so simple. I have 2 simulation models for a Via (created by 2 different tools). When I cascade 2 Vias in a channel, they give me pretty different answers in the (tdr/time/frequency domain). I have already designed and fabricated test boards that contain a variety of structures including single and cascaded vias. My question is if I wanted to build a library of via models and validate a sampling of them how would YOU go about designing test structures that were accurate to say 10G? Would you place a single via with short etch (that you de-embed), Would you cascade several vias, or something else ? Any Suggestions would be appreciated. Regards Bob haller Architect Enterasys Networks -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Yuriy Shlepnev Sent: Sunday, June 10, 2012 3:25 PM To: Ravinder.Ajmani@xxxxxxxx; si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Re: Measurement/Simulation Correlation Hi Ravinder, You have got some good advices already and I just wanted to elaborate a little on the validation of analysis with measurements (or the other way around). I have participated in a number of such projects with our partners and our experience and the results were reported and published at DesignCon every year since 2009 (papers and presentations are available at http://www.simberian.com/AppNotes.php - #2009_03, 2010_01, 2011_02, 2011_03, 2012_01). You have to develop a systematic approach to identify the limits of your tool on a set of structures typically used in your design. It obviously must start with the broadband dielectric and conductor roughness model parameters identification. Without such models any analysis is useless and you may end up with "tweaking" the material parameters to match the data. Worst case scenario is "tweaking" the parameters for every structure on the board if some physical effects are not included in the models (even geometry is "tweaked" some time). With the appropriate material parameters identification (with two line segments and GMS-parameters for instance), the analysis of typical structures on the board should correlate well with the measurements without any additional adjustment of the material model parameters. Deviation of measured data from simulated indicates either at the limits of the model, or geometrical difference of a model and actual board. If your vias for instance cannot be simulated in isolation from the rest of the board (not localizable), the analysis will always deviate from the measurements even with 3D electromagnetic modeling. The geometrical differences is the last resort if the discrepancies cannot be explained otherwise - the board may need cross-sectional investigation (you may find some surprises from you manufacturer). With a systematic approach in place and couple of iterations you will have a board with behavior that can be reliably predicted with your existing or newly selected tools. Note that the measurements may also need the validation, especially if de-embedding is involved. If you are not confident both in analysis and measurements, I would recommend you to get a board that was previously measured and simulated up to your target frequency - something like CMP-08 from Wild River Technology (http://wildrivertech.com/) featured in multiple DesignCon papers. Best regards, Yuriy Yuriy Shlepnev, Ph.D. President, Simberian Inc. 3030 S Torrey Pines Dr. Las Vegas, NV 89146, USA Office +1-702-876-2882 Cell +1-206-409-2368 Skype: shlepnev www.simberian.com -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Ravinder.Ajmani@xxxxxxxx Sent: Friday, June 08, 2012 3:59 PM To: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Measurement/Simulation Correlation Hi Experts, I have built a simple test board for correlating the simulated S-Parameter data (extracted using Ansoft SIwave) with VNA measurements. I get good Insertion Loss correlation up to 12 GHz, buy beyond that the measured Insertion Loss drops more significantly than the simulated data. I have tried tweaking the dielectric loss, but it does not help much. Could this added loss be due to surface roughness, which I have not taken in to account, or the tool limitation. I do get better correlation with the Mixed-Mode Insertion Loss (within 2 dB up to 20 GHz). I may add that my colleague generated S-parameter data on the same design using Agilent Momentum, which correlates well up to 16 GHz, but also shows resonances that don't show up in the measurements. It also correlates well with Mixed-Mode Insertion Loss. I will appreciate any lead in to this. Thanks. Regards Ravinder Ajmani HGST, a Western Digital company ravinder.ajmani@xxxxxxxx ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List forum is accessible at: http://tech.groups.yahoo.com/group/si-list List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List forum is accessible at: http://tech.groups.yahoo.com/group/si-list List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List forum is accessible at: http://tech.groups.yahoo.com/group/si-list List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu