Several points I'd like to make. Even though the software says that there is a 1 mil delta, that does not mean there is really a 1 mil delta. In every PCB layout tool that I am aware of, measurements are made from the origin point of one pad to the origin point of the other pad, through the centerline of the trace. If all parts are centered on the pads, this can be reasonably accurate. However, many surface mount devices with rectangular pads will contact the pads at various location off-origin. This results in significant error. An example of this might be TSOP memory devices. Traces are measured from the center of the track. However, the true path delay can be shorter (or longer) going around a bend, depending on whether the bend is predominantly inductive or capacitive. If the number of bends are not equal, and the direction of the bends between two traces are not equal, their delays will not be equal and significantly larger than 1 mil ( 170 fs in FR4). Another example might be traces crossing over or near antipads, where delay is altered. Another example is with serpentine traces. Crosscoupling between trace loopbacks can introduce significant delta in end-to-end delay. Ultimate, look at the numbers. 1 mil of stripline trace in FR4 has a delay of 170 femtoseconds. Does it make sense in any design to match something to accuracy that is beyond the propagation velocity uniformity of the underlying materials? Ultimately your FR4 has a variation of somewhere around 3 to 10 ps/inch. For my money, if traces are matched to within 50% of the underlying material uncertainty, I feel pretty good. That amounts to about a 50 mil trace matching requirement at the smallest (8.5 ps). If you're worried about EMI, don't be. Even if this was the maximum skew in a differential pair the 8.5 ps common mode pulse width would have maximum energy around 85 GHz. I'm pretty sure that most dielectrics will absorb that. Go ask your silicon designers just how well matched the outputs of their drivers are, and what the skew in the internal clock trees are. Ask the IC package designers how closely they matched the trace delays in their package, and how accurately they report those numbers back to you. And ask your material vendors what the lower bound of material Er variation is. Then justify the pain and suffering that a layout designer has to go through to match to within 1 mil or even 10 mils of trace length. I'm quite tired of lazy engineers not running the numbers and placing the burden on someone else. In most cases, if your design cannot withstand even 100 mils of trace length mismatch (17 ps of delay mismatch), you have a real serious problem with your design margins elsewhere, which you are not going to eliminate with ultra silly trace length matching. If you were a mechanical designer, designing components with a material that had the dimensional stability of rubber, and ask the machinists to mil it to within 1 mil tolerance, you'd be laughed out of a shop. respectfully, Scott Scott McMorrow Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 (401) 284-1827 Business (401) 284-1840 Fax http://www.teraspeed.com Teraspeed® is the registered service mark of Teraspeed Consulting Group LLC Bill Owsley wrote: > Jeff, > You said it much better than I was inclined to. > Thanks. > > As for leading edge designs using an auto-router, the guys spend nearly as > much time working the constraint table as it would take to lay it out by hand > and then it can be done over and over. But they still get those annoying > leftover nets that auto-router chokes on, reducing them to a miniumum is > their objective. > > "Loyer, Jeff" <jeff.loyer@xxxxxxxxx> wrote: > I think folks are missing Bill's point. I don't think he's saying that > the design is going to break at 2 mils routing difference, only that he > can easily attain a maximum 1 mil delta, so he uses that as his > constraint. If his CAD folks balked at that number, he'd probably > adjust accordingly and, if it got close to having significant impact, > would do a more detailed analysis. > > This is very similar to what we've done for common-clock FSB signals: > tell our CAD folks to match them within 10 mils (or some number), even > though we know we can absorb more. But, 10 mils is easily attainable, > and guarantees essentially no skew due to length differences. Granted, > it's a little more work on CAD's part, but the tradeoff is I don't have > to do a grand analysis to figure out exactly how close they HAVE to be > matched, and then worry about whether my analysis was correct (and > require subsequent validation in the lab, etc.).=20 > > This is about compromises, and where you put your energy into in-depth > analysis. If you can easily do 1 mil spacing, no problem. It's a > little tighter than I'd generally specify, but it's not absurd, either. > If you're using an auto-router (that's surprising to me, I didn't think > leading-edge designs could use them), you probably have different > constraints. > > Jeff Loyer > ------------------------------------------------------------------ > To unsubscribe from si-list: > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field > > or to administer your membership from a web page, go to: > //www.freelists.org/webpage/si-list > > For help: > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field > > > List technical documents are available at: > http://www.si-list.net > > List archives are viewable at: > //www.freelists.org/archives/si-list > or at our remote archives: > http://groups.yahoo.com/group/si-list/messages > Old (prior to June 6, 2001) list archives are viewable at: > http://www.qsl.net/wb6tpu > > > > > > --------------------------------- > Need a vacation? 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