[SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz
- From: "Dr. Edward P. Sayre" <esayre@xxxxxxxx>
- To: michael@xxxxxxxxxx, <mkhusid@xxxxxxxxxx>
- Date: Thu, 05 Sep 2002 10:48:10 -0400
Mike:
Series termination is particularly nice for point to point common clock
distribution since one need not know "How long" the clock traces are; that
is, with parallel termination, one has to know where the traces end.
If you are referring to "Bussed" clocking, then series terminated lines
offer the possibility that the incident half height signal (prior to
reflection) might induce a premature trigger. Bussed clocks are much rarer
than point to point common clocks, and in those cases where you need such a
bussed clock, design care must be exercised to avoid problems with series
termination. Usually, end point parallel termination is used, especially
if the bussed clock is on a backplane, where terminations are typically
located at the end of the bus. Bussed clocks are generally limited to
frequencies ~ 33 MHz rather than 100 MHz or above. The upper limit is set
by the architecture, chip set, AC parameters and clock to data skew, set-up
and hold requirements.
Sincerely,
ed sayre
===========
At 01:32 PM 8/16/2002 -0700, Michael Smith wrote:
>Hi,
>
>I have two questions related to reflective switching. First does
>reflective switching provide an easy termination scheme by only
>requiring series terminators at the drivers? This would drive half
>height waves down the line and full height would be achieved on the
>reflected pass.
>
>My second question is what do these schemes do for the clock. I
>wouldn't think you would want a half height clock traversing the line
>and hovering at the switching threshold. Do they drive a full height
>clock down the line? If not how do they avoid multiple clock edges?
>
>Thanks in advance,
>
>Michael Smith
>Hardware Engineer
>iZ Technology Corp.
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Michael Khusid
>Sent: Friday, August 16, 2002 12:50 PM
>To: 'Adeel Malik '
>Cc: 'si-list@xxxxxxxxxxxxx'
>Subject: [SI-LIST] Re: Matched Length Constaint Approximation for a bus
>running between 20-50MHz
>
>
>Adeel,
>
>The maximum flight time can be roughly calculated by formula:
>
>tflight_time < tperiod - tco - treceiver_setup - tcrosstalk - tjitter
>
>where tco is clock to output delay.
>
>The question is what is the flight time.
>
>Consider a bus with a driver and several receivers.
>
>Driver---Receiver1---Recever2--------------Recever3
>
>Most 20-50MHz buses today use reflective switching, so receiver1 has to
>wait
>for signal to travel from Driver to Receiver3 and back all the way.
>That's
>one full round-trip time delay. Also, such slow speed buses have no
>terminions (eg. PCI33), so it takes a few round trips for reflections to
>die
>out. In a conservative design, consider 5 to 10 round trips for a bus to
>quiet down.
>
>So, let's do a calculation.
>tperiod = 20ns
>tco = 2ns
>treceiver_setup = 2ns (I am guessing)
>tcrosstalk = 1ns
>tjigger = 0.5ns (guessing on last two)
>
>tflight time < 14.5ns
>Let's say you want to be conservative and allow for 10 round trips.
>round_trip_delay = 14.5/10 = 1.45ns
>line_delay = round_trip_delay / 2
>line_length = line_delay / speed = 0.5 * 1.45ns / 0.15 ns/inch =
>4.83inches
>
>Note that this is a very rough calculation. It gets more much more
>interesting with Ts/stubs on the line, connectors and terminations.
>Besides,
>there are no good ways to estimate time delay caused by crosstalk on the
>line. If you want to be more accurate, I would recommend using
>simulation
>software.
>
>Mike Khusid
>SI/HF Application Engineer
>Ansoft Corporation
>www.ansoft.com
>
>-----Original Message-----
>From: Adeel Malik
>To: si-list@xxxxxxxxxxxxx
>Sent: 8/16/02 8:14 AM
>Subject: [SI-LIST] Matched Length Constaint Approximation for a bus
>running
>between 20-50MHz
>
>
>Hi All,
> In order to accurately calculate the maximum lenght difference
>to
>meet the setup and hold times among the bus signals (address, control
>and
>data) , one needs to find the flight time of the traces, clock-to-output
>delay of the Flip-Flops and other logic involved ,cycle-time period and
>other things......
>But if someone is designing the bus for a 20-50MHz range, I don't think
>that
>there is any need to precisely calculate all the afore-mentioned
>parameters
>because I know that the cycle-time period for a bus running at e.g 50MHz
>is
>about 20ns while the delay of the outer-layer PCB Track is about 150
>ps/inch
>and clock to output delay of the flip-flop in the memory is about 1-2ns
>leaving at least 10-15ns of time-margin. So can someone give me any
>crude
>approximation to determine the maximum lenght difference among the
>microstrip traces running in 20- 50MHz range.
>Regads,
>ADEEL MALIK,
>
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