[SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz
- From: "Ingraham, Andrew" <Andrew.Ingraham@xxxxxx>
- To: <AdeelM@xxxxxxxxxxxx>
- Date: Fri, 16 Aug 2002 18:06:15 -0400
In most cases where there is a central clock distribution, there is no
need to match trace lengths of address, data, and control signals. They
just need to be long enough (no hold time violations) but not too long
(no setup time violations); so you should be thinking about them that
way, rather than with the objective to match lengths. (But you would
want to match the clock trace lengths.)
On the other hand, you might be concerned about matched lengths if the
bus uses some sort of local strobes, where you need to match the
address/data delays to those of the strobes.
If everything is very well controlled, and you know you can count on
incident wave switching, then it's possible to have very little delay
difference between identical length traces on the same layer. But
putting a limit on the delay difference is not so easy. I've seen
guesstimates of 10% of the total flight time range. For example, if the
board vendor says you'll see 140-190 ps/inch on some layer, that's 50
ps/inch total raw delay variation (incident wave, board to board); so
one might estimate 5 ps/inch difference between IDENTICAL traces on the
SAME layer of the SAME board.
Regards,
Andy
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