[SI-LIST] Re: Matched Length Constaint Approximation for a bus running between 20-50MHz
- From: Michael Khusid <mkhusid@xxxxxxxxxx>
- To: 'Adeel Malik ' <AdeelM@xxxxxxxxxxxx>
- Date: Fri, 16 Aug 2002 15:49:48 -0400
Adeel,
The maximum flight time can be roughly calculated by formula:
tflight_time < tperiod - tco - treceiver_setup - tcrosstalk - tjitter
where tco is clock to output delay.
The question is what is the flight time.
Consider a bus with a driver and several receivers.
Driver---Receiver1---Recever2--------------Recever3
Most 20-50MHz buses today use reflective switching, so receiver1 has to wait
for signal to travel from Driver to Receiver3 and back all the way. That's
one full round-trip time delay. Also, such slow speed buses have no
terminions (eg. PCI33), so it takes a few round trips for reflections to die
out. In a conservative design, consider 5 to 10 round trips for a bus to
quiet down.
So, let's do a calculation.
tperiod = 20ns
tco = 2ns
treceiver_setup = 2ns (I am guessing)
tcrosstalk = 1ns
tjigger = 0.5ns (guessing on last two)
tflight time < 14.5ns
Let's say you want to be conservative and allow for 10 round trips.
round_trip_delay = 14.5/10 = 1.45ns
line_delay = round_trip_delay / 2
line_length = line_delay / speed = 0.5 * 1.45ns / 0.15 ns/inch = 4.83inches
Note that this is a very rough calculation. It gets more much more
interesting with Ts/stubs on the line, connectors and terminations. Besides,
there are no good ways to estimate time delay caused by crosstalk on the
line. If you want to be more accurate, I would recommend using simulation
software.
Mike Khusid
SI/HF Application Engineer
Ansoft Corporation
www.ansoft.com
-----Original Message-----
From: Adeel Malik
To: si-list@xxxxxxxxxxxxx
Sent: 8/16/02 8:14 AM
Subject: [SI-LIST] Matched Length Constaint Approximation for a bus running
between 20-50MHz
Hi All,
In order to accurately calculate the maximum lenght difference
to
meet the setup and hold times among the bus signals (address, control
and
data) , one needs to find the flight time of the traces, clock-to-output
delay of the Flip-Flops and other logic involved ,cycle-time period and
other things......
But if someone is designing the bus for a 20-50MHz range, I don't think
that
there is any need to precisely calculate all the afore-mentioned
parameters
because I know that the cycle-time period for a bus running at e.g 50MHz
is
about 20ns while the delay of the outer-layer PCB Track is about 150
ps/inch
and clock to output delay of the flip-flop in the memory is about 1-2ns
leaving at least 10-15ns of time-margin. So can someone give me any
crude
approximation to determine the maximum lenght difference among the
microstrip traces running in 20- 50MHz range.
Regads,
ADEEL MALIK,
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