[SI-LIST] MPX bus impedance

From: "Santangelo, Steven" <SSantangelo@xxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Mon, 5 Mar 2007 19:21:09 -0500

I'm looking at an MPX bus implementation with a single PowerPC and a
Xilinx FPGA.   The bus is currently routed at 50ohms.  The simulations
look pretty good but look a little better (over and undershoot wise) by
lowering the impedance, say to 45ohms or even 40ohms.  My board stack-up
supports the line width needed for the lower impedance and routing the
wider lines does not appear to be a problem.  Because of the large
number of signals and the bi-directional bus, adding terminations is not
a great option.  
 

I was wondering what are the issues related to changing this portion of
the design to the lower impedance?

 

Thanks

 

Steve

 

 


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[SI-LIST] MPX bus impedance

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