[SI-LIST] Re: METASTABILITY
- From: "Tran, Deanne (FL51)" <deanne.tran@xxxxxxxxxxxxx>
- To: "'dhavala.somesh@xxxxxxxxx'" <dhavala.somesh@xxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Mon, 9 Jan 2006 06:06:01 -0700
All flip flops have setup and hold time requirements for the data input
relative to clock input transition (usually flip-flop clock input is
rising-edge sensitive). If new data is presented to the flip flop in
advance of the clock input rising edge, meeting the setup time requirement,
and held beyond the clock input rising edge in accordance to the data-hold
time specifications, then the new data presented to the flip-flop data input
will be clocked into the flip flop and propagate to the flip-flop output
(call this time tco) within the specified propagation time, tco_max.
If the setup time (tsu) and hold time (th) specifications are not met, there
is a probability that tco will increase substantially, exceeding tco_max.
This is due to the flip flop operating metastable, and the time for the flip
flop to resolve the metastability is tr. Time tr can range from hundreds of
pS to tens of uS.
For any particular device (flip flop) due to manufacturing process,
operating at a particular voltage and at a particular temperature, there
exists a narrow window of time, tw, located within the time interval bounded
by device specifications tsu and th, where the specific device's
metastability is significant. For modern devices, the time window tw may
range from perhaps a hundred fS to tens of pS, and is largely a function the
flip flop technology.
Flip flops made with fast transistors having high gain-bandwidth product
have minimal tw and tr, which minimizes the metastability effect because the
likelihood of data input transitioning within tw is minimized, and even if a
data input transition did occur with the critical time interval tw, the
flip-flop transistors will quickly resolve the metastability to a high or
low state at the flip-flop output.
Other circuit-design solutions to preclude metastability due to asynchronous
data presented to the flip-flop data input include cascaded flip flops to
form a multi-stage synchronizer. The probability that the last synchronizer
stage output will be metastable decreases markedly as the number of
synchronizer stages increases (and as expected, a function of the flip-flop
speed and system (synchronizer) clock period). The probability that the last
synchronizer stage output will be metastable is P^n, where P is the
probability of the first flip flop remaining metastable for its clock
period, and n is the number of synchronizer stages. Typical synchronizers
are 2 or 3 stages; this is usually sufficient to increase synchronizer
output MTBF to a level well beyond system MTBF.
Deanne Tran
Honeywell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Somesh Dhavala
Sent: Thursday, January 05, 2006 9:54 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] METASTABILITY
Hi All,
I am very new to the SI.
I am unable to understand the concept of *METASTABILITY*, I am very thank
ful to you if you explain me in detail.
Please suggest me some documents.
Thanks & Regards
Somesh Dhavala
CG-CoreEl
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