[SI-LIST] Re: Lumped vs. Distrbuted systems.
- From: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
- To: scott@xxxxxxxxxxxxx
- Date: Wed, 15 Jan 2003 08:10:56 -0800
Michael,
An additional clarification. Below I said:
If a simulator uses the case 1) assumption for
modeling, then you will see typical RLC circuit ringing in the waveforms
for fast risetimes. But, if the simulator uses the case 2) assumption,
and the package impedance is close to the PCB impedance, then the system
will simulate in a more "distributed" fashion, and you will see only the
appropriate ringing for that particular total system electrical length.
In addition, there is another possibility. If the simulator uses the
case 2) modeling assumption of a distributed circuit, and there is
significant mismatch between the package impedance and the PCB
impedance, then there will also be high frequency ringing. This is real
and can be measured in fast systems. In that case, the distributed
transmission line model of the package has a higher qualtity factor than
lumped RLC modeling and will often show greater amplitude ringing. As a
first approximation for a device package, this is also close to reality.
The distributed model is "usually" more faitiful to the actual circuit
response.
Ultimately, for high speed, fast risetime, designs we need to steer away
from simplistic modeling such as either approach. Packages should
generally be modeled with coupled multi-line models that are currently
beyond the capability of IBIS. However, a new IBIS specification that
is in committee can be used for modeling packages more accurately when
it is introduced. It will allow the insertion of Berkley Spice and
VHDL-AMS circuits into an IBIS simulation environment.
BIRD75.8 - Multi-Lingual IBIS Model Support
Packages are much more complex beast that we sometimes give them credit
for in our simulations.
best regards,
scott
--
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
Scott McMorrow wrote:
>Michael,
>
>The answer is: if the total electrical path length is shorter than a
>reasonable fraction of the rise time, the system will appear to be
>lumped. In reality, reflections are always occuring. Even a .1 inch
>line will establish a reflection, and this reflection will occur after
>the signal has reached the end of the line. But in FR4 that reflection
>would occur 18 ps after the driver launch and be returned to the driver
>36 ps after the launch. This will for all purposes appear to act as a
>lumped circuit.
>
>As for your simulator issue, I am going to assume that you are using
>IBIS models for your components. First, remember that the package
>itself has additional electrical length, and may be as long as 100 ps or
>more, depending upon the device. Second, most IBIS package models
>contain only LRC elements for the package parasitics, even though more
>advanced package modeling is available through the [Package Model]
>construct.
>
>Now, assuming that the model is an IBIS model and that the package is
>defined only using one set of LRC elements, we can look hypothetically
>at the simulator issue. IBIS does not specify how the LRC package
>parasitcs are to be simulated. There are two choices.
>
>Case 1) Simulate using a lumped L, R and C circuit between the die and
>the package pin.
>Case 2) Simulate using the distributed equivalent of the L, R and C
>parameters.
>
>In reality, packages are really distributed transmission line circuits,
>not lumped RLC circuits. So the lumped RLC approximation is only valid
>for slow rise times. If a simulator uses the case 1) assumption for
>modeling, then you will see typical RLC circuit ringing in the waveforms
>for fast risetimes. But, if the simulator uses the case 2) assumption,
>and the package impedance is close to the PCB impedance, then the system
>will simulate in a more "distributed" fashion, and you will see only the
>appropriate ringing for that particular total system electrical length.
>
>It turns out that the simulators which model the package parasitics as a
>distributed transmission line are much more faithful to the "real"
>measured waveform, for fast risetime signals. Whereas the simulators
>which model the package parasitics as lumped elements tend to exhibit
>more ringing. Finally, if you are simulating with HSpice B-elements for
>IBIS models, then be aware that the package is not modeled at all. You
>need to add that into your circuit.
>
>To test these assumptions in your IBIS simulators, create a modified
>IBIS model with absolutely no package parasitics. L, R and C = 0. Then
>run your simulations again. In this case, all the simulators should
>match, unless there is a difference in the waveform simulation
>algorithm, or the transmission line modeling algorithm. Then run the
>original model and note the differences. If the difference is high
>frequency ringing, at about the period which would occur with a lumped
>RLC, then you have identified which simulator is using lumped RLC
>modeling for the package. You can also perform this experiement in
>HSpice with the B-element and two cases. In the first case, model the
>package with discrete R, L and C elements. In the second case, model
>the package with a transmission line equivalent. For the transmission
>line equivalent use the following equations to determine your T-line
>parameters:
>
>Z = sqrt(L/C)
>delay = sqrt(LC)
>
>It is always possible that the PCB transmission line modeler is using
>lumped LRC sections, but this is highly unlikely these days. Most PCB
>SI simulators that I know of these days use distributed transmission
>line modeling for the traces.
>
>best regards,
>
>scott
>
>
>
>
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