[SI-LIST] Re: Lumped capacitance estimation
- From: Istvan Novak <istvan.novak@xxxxxxx>
- To: sushil.gupta@xxxxxx
- Date: Thu, 07 Apr 2005 07:47:57 -0400
Hi Sushil,
Assuming no losses, and perfect matching throughout from
driver to load, the driver will see a resistive load, which
equals the characteristic impedance of the line. This means
that if the driver achieves 600ps rise/fall times across a
lumped 10pF load, you may see faster edges if you connect
a perfectly matched lossless transmission line to the driver.
If you have mismatches anywhere along the way, the input
impedance shown to the driver will be frequency dependent,
and periodically as frequency changes it may contain capacitive
or inductive reactances. siomple SPICE simulations, or in case
of simple topologies, solving the analytical input-impedance
formula, should give the numeric answer. Losses will help
to reduce the reflection and the input reactanes coming from
mismatch.
The above assumes a pure cascaded linear topology. Anything beyond
that (like via stubs, active device inputs/outputs) have to be
considered as extras.
Best regards,
Istvan Novak
SUN Microsystems
Sushil Kumar GUPTA wrote:
>Hi Andrew,
> Perhaps I couldn't explain the problem in right way.
> Suppose you have a transmission line (cable) which is
>very long let's say 30ns delay. If we assume cable has no loss then
>whatever waveform you apply, you will get FAR-END wave after 30ns delay.
>I am assuming both end are perfectly matched.
> Now if you cansider the NEAR-END rise/fall time (let's assume
>avg value 600ps) , it will not depend on the length of the cable. So my
>question is that waht will be the approximate value of capacitive load
>at the NEAR-END (this time no cable is used) which will provide the same
>rise/fall time achieved with cable.
> I can state the problem in a different way also. Let's assume
>that IO driver has 600ps rise/fall time with 10pf capacitive load. If I
>increase the capacitive load obviously rise/fall time will increase.
> The PCB trace has 2.72pf/inch capacitive load. If now I connect cable(
>PCB trace) with IO driver, it will see 2.72pf/inch capacitve load. The
>driver has 45Ohm dc impedance w.r.t ground. So when driver starts
>charging PCB trace, every inch of trace will be charged, but only that
>part of PCB trace will impact the rise/fall time which is travelled
>during transition time. So how will I know how many inches to be
>considered.
>Andrew Ingraham wrote:
>
>
>
>>> I need to calculate equivalent lumped capacitance seen by an IO
>>>driver which is connected to PCB trace (approx 3 Inches) and then cable.
>>>The average rise/fall time is 600ps. I have information about the PCB
>>>trace capacitance/inches. Will my assumption be correct if I take
>>>PCB-trace length (for lumped-capacitance calculation) which provides 300ps
>>>delay.
>>>
>>>
>>>
>>>
>>For lumped capacitance, just multiply capacitance/length times the length.
>>
>>The rise/fall time doesn't make any difference as far as equivalent lumped
>>capacitance is concerned. However, if the rise/fall time is fast enough,
>>you shouldn't be using a lumped capacitance in simulations.
>>
>>Are you sure your PCB trace delay is only 100ps/inch?
>>
>>
>>
>>
>>
>>>What would be the best way to simulate IO driver as far as rise/fall time
>>>accuracy is concerned assuming lumped model for Tx line.
>>>
>>>
>>>
>>>
>>For accuracy, best way = abandon the lumped model for the line.
>>
>>What did you mean by "best way" anyway? If you have an I/O driver model and
>>a transmission line model, just simulate them and look at the results.
>>
>>Regards,
>>Andy
>>
>>
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>
>
>
>
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