[SI-LIST] Re: Lumped capacitance estimation
- From: Sushil Kumar GUPTA <sushil.gupta@xxxxxx>
- To: naren@xxxxxxxxxx, si-list <si-list@xxxxxxxxxxxxx>
- Date: Wed, 06 Apr 2005 18:29:16 +0530
Hello Naren,
I am doing spice simulation with
Mentor-graphics' tool "ams". It is device level simulation. I do not
have model for PCB trace. I just want to correlate the spice result
obtained using lumped approximation with the actual results obtained
from silicon with PCB trace. I do have the complete die/package model.
Even if an instruments does input capacitance measurement for
any port on PCB, does it take into account the signal rise/fall time
for the approximation.
Naren wrote:
>Hi Sushil
>
> Which tool you are using for simulation?
>
>
>Sushil Kumar GUPTA said:
>
>
>>Hi all,
>> I need to calculate equivalent lumped capacitance seen by an IO
>>driver which is connected to PCB trace (approx 3 Inches) and
>>then cable. The average rise/fall time is 600ps. I have
>>information about the PCB trace capacitance/inches. Will my
>>assumption be correct if I take PCB-trace length (for
>>lumped-capacitance calculation) which provides 300ps delay.
>> What would be the best way to simulate IO driver as far as
>> rise/fall
>>time accuracy is concerned assuming lumped model for Tx line.
>>
>>Thanks
>>sushil
>>
>>====================================================
>>Beat indecision and you beat the clock.
>>
>>
>>
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