[SI-LIST] Re: Low Temperature Limit
- From: "Tom Dagostino" <tom@xxxxxxxxxxxxx>
- To: <jkeeble@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 16 May 2005 00:11:30 -0700
Jon
There are several characteristics that may dictate the lower limit for a
device. Silicon characteristics are only one. I'll bet the dominate one is
mechanical, can the package/die interface tolerate the temperature extreme?
Will the CTE cause the die to break away from the package?
As you know CMOS devices get faster at lower temperature whereas bipolar get
slower. Will a lower limit cause a part to go out of specification? Or stop
functioning?
Tom Dagostino
Teraspeed Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065
http://www.teraspeed.com
tom@xxxxxxxxxxxxx
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827
Teraspeed is the registered service mark of
Teraspeed Consulting Group LLC
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Jon Keeble
Sent: Sunday, May 15, 2005 11:56 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Low Temperature Limit
On this list, all signals are analog. So, hereabouts, what do you call a
signal that is actually .. analog?
First question (a bit off topic for this group): what determines the lower
operating temperature of a silicon circuit? For instance, TI specifies the
OPA2134 opamp from -55C to 125C. Is -55C as cold as it seems reasonable to
measure, and the part will work down to liquid nitrogen? or does something
stop working.
Second question: why don't vendors specify noise / jitter as a function of
temperature? A brief reading in the ieee electron devices department
indicates that drain noise and other 'excess' noise in FETs is '4kT' style
noise.
These questions came up in the low frequency analog domain, but maybe
relevant in Gbit circuits (?).
Regards
Jon Keeble
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