[SI-LIST] Re: Lout of VRM
- From: Larry Smith <Larry.Smith@xxxxxxx>
- To: si-list@xxxxxxxxxxxxx, sghsu55@xxxxxxxxxxxx
- Date: Thu, 15 Aug 2002 09:42:44 -0700 (PDT)
Sogo - Be careful not to mix up the inductance in a macro model of a
VRM and the inductance of the working inductor in a buck switching
regulator. They are two very different things. It sounds as if you
are looking at the simulation results of a high level macro model for a
VRM and inferring something about the design for the VRM. This is not a
good thing to do.
A full cycle by cycle simulation of a switching power supply is very
complex. It may take CPU hours to simulate all of the components that
make up the FET switches, working inductor, control loop, etc. But
this is what has to be done to really understand regulation loop
performance and stability. It is far too complex of a simulation to
include in a PDS analysis where we really only want to know the output
characteristics of the VRM so that we can size the system bulk and high
frequency capacitors that must be used to maintain a a target
impedance.
In a paper (ref below), I proposed a high level macro model for the VRM
that involved just 4 linear components: L_slew, R_flat, L_out and R0.
The subject line of this email leads me to believe that you may be
using at least a portion of that model for your PDS simulation. L_out
is actually the inductance associated with the connector for the VRM,
not the working inductor. L_slew is roughly correlated with the
working inductor of the buck regulator but no attempt should be made to
infer the value of the working inductor(s) from this high level
simulation.
L_slew is simply calculated by knowing the number of uSec that it takes
for the buck regulator to slew the maximum transient current for the
VRM (large signal dI/dt). By knowing that the output of the VRM must
stay within some voltage margin (5% of Vdd), we can calculate a high
level macro model value for L_slew from the V = L di/dt equation:
L_slew = Vdd*5% * dt/dI
This is an inductance suitable for a high level macro model for the
VRM. It indicates the amount of time necessary for the VRM to respond
to a current transient. No attempt should be made to adjust the value
of the working inductance in the VRM as a result of simulation with the
high level macro model. Adjustments to the working inductance can only
be made after careful simulation of the full cycle by cycle model of
the VRM or by other means for evaluating the stability and performance
of the regulation loop.
regards,
Larry Smith
Sun Microsystems
ref: "Power Distribution System Design Methodology and Capacitor
selection for Modern CMOS Technology," IEEE Transactions on Advanced
Packaging, August, 1999 pp284-291, by a bunch of authors at Sun. A
soft copy of the original manuscript is found under
http://groups.yahoo.com/group/si-list/files/
Look for the cpmt_1999.pdf paper in the Sun section.
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> From: "sogo_hsu" <sghsu55@xxxxxxxxxxxx>
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Lout of VRM
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>
> Istvan,
>
> Thank you for your response. I know the effect of violation in
> target impedance. However, actually, it is hard to find a proper
> inductor to match the specification of today's PDS. In contrast, If I
> used a shorted inductor instead of 1 uH, will VRM and/or PDS work
> properly?
>
> Best regards,
>
> --- In si-list@xxxx, "istvan novak" <istvan.novak@xxxx> wrote:
> >
> > Sogo,
> >
> > If you dont change anything else, only the inductor will be of
> > ten times lower value, the ripple current through the inductor
> > will be ten times higher. If otherwise the 1uH inductor was
> > properly designed for the application, the ten times higher
> > ripple current will most probably drive its core to saturation
> > or at least the losses will increase significantly. If you see
> > a 1kHz peak in the impedance profile with 1uH output
> > inductor, the probable cause is a suboptimal control loop.
> >
> > regards
> >
> > Istvan Novak
> > SUN Microsystems
> >
> > ----- Original Message -----
> > From: "sogo_hsu" <sghsu55@xxxx>
> > To: <si-list@xxxx>
> > Sent: Wednesday, August 14, 2002 10:35 AM
> > Subject: [SI-LIST] Lout of VRM
> >
> >
> > >
> > > Hi SI Gurus,
> > > Firstly, I have got lots of help from this forum; I have to say
> > > thank you to all give me advises in advance. Recently, I had done
> > > several simulation works regarding PDS design. We computed the
> > > impedance of PDS including the model of VRM. Roughly said, the
> VRM is
> > > almost three-phase type and with 1uH inductor type we adopted.
> That
> > > is said, the equivalent output inductance is 0.333uH. The
> simulation
> > > result indicated the impedance of PDS has a peak violates the
> > > specification of target impedance at about 1 kHz. We proposed
> > > dwindling the inductor from 1 uH to about 100 nH to match the
> > > specification of target impedance. However, it is hard to find
> the
> > > proper component to match the requirement. I have some questions
> > > regarding the simulation work.
> > > (1) What=A1=A6s the role of output inductor in VRM? It seems
> lower
> > > output inductor of VRM makes up lower impedance of PDS. So,
> what=A1=A6s
> > > the aftereffect if a low output inductor, even we shorten the
> output
> > > inductor, was adopted?
> > > (2) If we ignore the violation at about 1KHz due to the
> > > =A1=A5high=A1=A6 inductor, what=A1=A6s happen in PDS design?
> > > Thank you for your helps in advance.
> > > Best regards,
> > > Sogo Hsu
> > >
> > >
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