[SI-LIST] Re: Looking for books, classes or instructions on microvias for hi-layer count designs
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "Viklund, Per" <Per_Viklund@xxxxxxxxxx>, "kevin kimball" <kkimball28@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Sat, 5 Nov 2011 10:35:33 -0700
Good book. Just beware that HDI is not a good choice if you have
components that allow you to have through hole vias. In this case, it does
not turn out to save layers as claimed. Just makes the board harder to
design, fabricate and test. I've got several examples of this.
Lee
--------------------------------------------------
From: "Viklund, Per" <Per_Viklund@xxxxxxxxxx>
Sent: Friday, November 04, 2011 1:29 PM
To: "kevin kimball" <kkimball28@xxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: Looking for books, classes or instructions on
microvias for hi-layer count designs
> Slightly biased, I'd like to suggest the HDI handbook -free PDF download
> 0ver 600 pages in the topic.
>
> /Per
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of kevin kimball
> Sent: den 4 november 2011 21:22
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Looking for books, classes or instructions on microvias
> for hi-layer count designs
>
> Hi All,
>
> I have designed PCB's for over 15 years using Cadence and Mentor Graphics
> Boardstation. I have not had the opportunity
> to layout hi-layer count PCBs using microvias. So does anybody know if
> there are any books, classes or may-be PDF instructions that will push me
> in the right direction?
>
> Thanks,
>
> Kevin (San Diego, Ca.)
>
> ________________________________
> From: Jayasuryan KG <suryan_tvm@xxxxxxxxxxx>
> To: si-list@xxxxxxxxxxxxx
> Cc: Doug Smith <doug@xxxxxxxxxx>
> Sent: Wednesday, November 2, 2011 4:09 AM
> Subject: [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB
>
> Dear All,
>
> Thanks for your valuable inputs. Basically I would like to go with
> conservative stack up to avoid any kind of issues
> in the initial proto type. After your valuable suggestion(s), I am
> planning
> to reduce the number of layers from 10 to 8.
>
> Any suggestion in the new stack-up?
>
> Best Regards,
> Jayasuryan
>
> -----Original Message-----
> From: Doug Smith
> Sent: Wednesday, November 02, 2011 10:27 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB
>
> The cost of a product stop ship or delayed introduction can be in the
> millions of $. I prefer to be conservative and then back off as soon as
> things are out and working properly. I see disasters all the time caused
> by reducing cost on the first design. If one has a lot of experience
> with nearly identical designs (similar circuit boards in similar
> enclosures), then one can draw on that to take risks.
>
> A company I used to work for went under (about 1 1/2 years after I left
> them) because of a risk that was taken resulting in a stop ship on all
> of the company's products that lasted a whole quarter. It was a signal
> integrity issue. The company survived the incident but the lost cash set
> the stage for later problems.
>
> BTW, using a magnetic field probe I made from a paperclip, I found the
> problem in a few hours work (not actually my job, just helping the
> team), but the lead engineer would not believe such a simple method was
> valid so he took a month to find the problem with a lot of expensive
> test equipment. At some point I may do a WebEx session on this method
> which I have further developed over the years. If you might be
> interested in this, contact me privately.
>
> Magnetic field probes are not normally used for signal integrity
> measurements. But in this case, such a probe was able to permit
> measuring a critical noise voltage in the circuit that turned out to be
> the problem.
>
> Doug
>
> On 11/1/11 3:49 PM, Lee Ritchey wrote:
>> Cost!
>>
>> From: Jory McKinley
>> Sent: Tuesday, November 01, 2011 12:55 PM
>> To: Lee Ritchey ; Filion, Marc-Andre
>> Cc: si-list@xxxxxxxxxxxxx
>> Subject: Re: [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB
>>
>>
>>
>>
>> Same number of layers much much better noise/resonance isolation, where
>> is the downside?
>>
>>
>>
>>
>>
>> --------------------------------------------------------------------------------
>> From: Lee Ritchey<leeritchey@xxxxxxxxxxxxx>
>> To: Jory McKinley<jory_mckinley@xxxxxxxxx>; "Filion,
>> Marc-Andre"<marc-andre.filion@xxxxxxxxxxxxxx>
>> Cc: si-list@xxxxxxxxxxxxx
>> Sent: Tuesday, November 1, 2011 3:27 PM
>> Subject: Re: [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB
>>
>> Way too many ground planes.
>>
>> --------------------------------------------------
>> From: "Jory McKinley"<jory_mckinley@xxxxxxxxx>
>> Sent: Tuesday, November 01, 2011 9:02 AM
>> To: "Filion, Marc-Andre"<marc-andre.filion@xxxxxxxxxxxxxx>
>> Cc:<si-list@xxxxxxxxxxxxx>
>> Subject: [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB
>>
>>> My post are showing up either without content or partial? Hopefully
>>> this
>>> one post correctly. This is the stack-up I would consider for
>>> Jayasuryan
>>> board:
>>>
>>> TOP
>>>
>>> GND
>>> DVDD1_2/D2VDD1_2/DVDD1_8
>>>
>>> GND
>>>
>>> SIG1/SIG2
>>>
>>> SIG3/SIG4
>>>
>>> GND
>>>
>>> DVDD5/DVDD3_3
>>>
>>> GND
>>>
>>> BOTTOM
>>>
>>>
>>> Regards,
>>> -Jory
>>>
>>>
>>>
>>>
>
> --
> -------------------------------------------------------
> ___ _ Doug Smith
> \ / ) P.O. Box 1457
> ========= Los Gatos, CA 95031-1457
> _ / \ / \ _ TEL/FAX: 408-356-4186/358-3799
> / /\ \ ] / /\ \ Mobile: 408-858-4528
> | q-----( ) | o | Email: doug@xxxxxxxxxx
> \ _ / ] \ _ / Website: http://www.dsmith.org
> -------------------------------------------------------
>
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