[SI-LIST] Re: Leaving, then re-entering a reference plane
- From: Richard Jungert <r_jungert@xxxxxxxxxxx>
- To: D MAC <dhwn@xxxxxxx>, si list freelist <si-list@xxxxxxxxxxxxx>
- Date: Wed, 1 Jul 2009 09:03:19 -0700
Don.
Take some time and study the schematic real well to get the idea which signals
belong to which planes. Signals and plane have to match schematic and match in
the layout.
All of that information has to be in the schematic. In most cases the
principal engineer on the project can or hopefully is available to support
this. Talk to the engineers and ask good questions. Remember, there is no
such thing as a dumb question.
Richard Jungert
> Date: Wed, 1 Jul 2009 10:09:54 -0400
> From: dhwn@xxxxxxx
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Leaving, then re-entering a reference plane
>
> Hello,
>
> I have a question about the effects of a split reference plane on a signal
> that starts and ends referenced to the same plane, but encounters a second
> plane along the way. Here's a shot of what I'm talking about:
>
> http://idisk.me.com/dhwn/Public/split_plane.png
>
> All of those signals are part of a source-terminated QDRII (200 MHz) data
> bus. In this part of the stackup, the signals are on one layer of a
> dual-stripline. The other plane forming the stripline is a solid ground, and
> there is no solid ground plane adjacent to the split power plane shown. There
> are no capacitors between the two shown power planes. (yes, lots of things
> wrong there! :-)
>
> Leaving aside the lesser effect of the more distant solid ground plane in the
> dual-stripline, what happens to the return currents for these signals? I
> assume that the majority of the current flows on Plane 1 around the split
> back to the drivers as shown, but the presence of the signal over Plane 2
> must certainly induce a current there, and that's injecting energy into a
> place that is not intended. Plane 2 is well decoupled in that vicinity (you
> can see vias attached to the plane there--these are decoupling caps) so I'd
> like to think that at least medium frequency energy has a path to the gnd
> plane (and back to the driver, if a bit circuitously), but what of the higher
> frequency energy for which that path is too inductive? I'm still a little new
> at this and I'm having trouble "being the signal", as Eric Bogatin might say.
> :-)
>
> As for crosstalk, these signals are all members of the same bus (clock not
> included), and there is a relatively large timing margin to work with. My
> working assumption is that the majority of the return current will flow
> around the split on Plane 1, so these signals will all inductively
> couple--but since they are all members of the same bus and since there is
> large margin, I'm only moderately concerned by the edge distortion that will
> occur as a result. The only issue is that I'm a little fuzzy on how to
> *quantify* the amount of distortion to be sure that it doesn't totally eat up
> the rest of the margin--I don't have a simulator that can deal with return
> paths and am still too much of a newbie to find a back-o-the-envelope
> estimate. I am also making the assumption that the impedance discontinuity
> over each void is small compared with the edges of the signal.
>
> EMI? I'm not even sure where to begin predicting that! (that split plane is
> layer 2, and layer 1 is a surface microstrip... I've got a bad feeling about
> this!)
>
> Thanks in advance to everyone who helps shed some light on this,
>
> Kind regards,
> Don Nelson
> Netronome Systems
>
> --
> Don Nelson
>
> "The whole problem with the world is that fools and fanatics are so sure of
> themselves, and wiser people so full of doubt" --Bertrand Russell
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