[SI-LIST] Re: LVDS center tap capacitor termination
- From: "Ummalaneni, Venu Babu (Venu)" <venubabu@xxxxxxxxx>
- To: "steve weir" <weirsp@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 30 Aug 2004 16:16:06 +0530
Steve,
I think as a differential scheme, LVDS inherently rejects the common
mode signal/noise. I mean whatever that is common on both traces with
respect to the reference plane/ground.=20
So what is the extra advantage of using 'center tap scheme'?
Best regards,
Venu Babu
-----Original Message-----
From: steve weir [mailto:weirsp@xxxxxxxxxx]=20
Sent: Monday, August 30, 2004 3:49 PM
To: Ummalaneni, Venu Babu (Venu); si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] LVDS center tap capacitor termination
The two resistor termination is a double single-ended termination. The=20
single resistor termination presumes a virtual ground at the center of
the=20
resistor.
What noise sources do you think LVDS is trying to reject?
What noise sources do you think LVDS can reject?
What noise sources do you think LVDS cannot reject?
Steve.
At 03:34 PM 8/30/2004 +0530, Ummalaneni, Venu Babu (Venu) wrote:
>Hi=3D20
>
>This query is regarding termination schemes at the LVDS receiver=20
>inputs.
>
>Can some one explain me the difference between a 'single resistor=20
>termination' and 'the two resistors with center tap capacitor' ?
>
>I read some where that the 'center tap capacitor scheme' filter's the=20
>common mode noise. My doubt is that even in 'single resistor scheme'=20
>also if we run the differential traces verly closely the common mode=20
>noise pick-up by the two traces is equal and the Receiver can reject=20
>this common mode part, right? So why we need to go for center tap=20
>capacitor scheme? It unnecessarily increase the component count on the=20
>board, right?
>
>Any inputs are appreciated.
>
>Best regards
>Venu Babu.
>
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