Shawn, Short answer - talk to your assembly house to be 100% sure you make the right choice: communication at an early stage is important in any case, to help optimise the assembly and so avoid unnecessary costs. Long answer - normally, I would recommend either: a) plugged, capped, tented or flooded vias in the heatsink pad, or b) open vias (as many as possible) directly on the edge of the pad, BUT with a min. 0.1mm line of solder mask between the thermal pad copper and exposed via hole (particularly if you're using the LDO well within spec). The best solution is plugging as well as plating over the vias, if you can afford it - then you can really fill the heatsink with vias, and get 100% direct contact between heatsink and board without running the risk of voids (voids meaning less than 100% of the heatsink is in direct contact with the board). Plugging is kind of overkill, however, if you're just plugging the one LDO footprint on a big board! Talk to your board manufacturer, and see what possibilities he has to offer, and what the costs are: plugging can be surprisingly affordable, depending upon the manufacturer. At any rate, either solution will avoid solder running into the vias. The problem in this case with solder run is, in comparison to a small component, not so much that you run the risk of having a dry joint by placing open vias in the heatsink pad; rather, you will almost certainly have small 'pips' of solder sticking out the other side of the vias which will impede solder paste application on the 2nd side (assuming the board is reflow-soldered on both sides). This can be a very serious problem if the board is full, especially in the case of fine pitch components on both sides. If, however: a) the board is only assembled on 1 side (unlikely, right ;-)!?), OR b) you can place the LDO on the 2nd side (it's generally a good idea anyway to assemble all large, heavy components on one side, which will then be the 2nd reflow side) AND the vias are small, OR c) the 2nd side will be wave-soldered (likely if there are a number of through-hole components present), then you should be able to leave the vias open. That said, keep the following in mind: with a lot of open vias in the pad, even if it's not a problem for the assembly, you will get some degree of voiding in the heatsink solder, which will, of course, _increase_ thermal resistance, the exact opposite of what you are trying to achieve with the vias! Voiding also decreases, to some degree, mechanical stability, although this may not be a major concern. My last comment: if you're using the LDO close to the limit, then IMHO relying on the vias and board as a heatsink to keep the component operating inside the spec, particularly without knowing precisely what the thermal resistance of the mounted component on such an untested footprint is, is a risky business - the worst case is, of course, that the component DOESN'T burn out directly while you're testing, but after a few weeks/months once the product is out in the field!! Regards, Sol STaylor5@xxxxxxxx schrieb: > All, > > We have a TI LDO (TI1963A-25KKT) in a KTT package (9.65mm x 10.67mm thermal > pad), but we don't have the space on our (16 layer) board for the required > 50mm x 50mm copper pours on the top and bottom. We're hoping to use the > internal GND planes to help dissipate the heat away from this component, and > have placed some vias *nearby* the LDO pad for this purpose. > > Wondering if placing vias right in the ground pad under a chip of this size > is going to cause any issues with the soldering process? Certainly the > contact with the ground planes in our stack is improved if the heat can > travel direct instead of only through the neighboring vias. > > Any experience/insights would be appreciated. > > Kind Regards, > > Shawn > > ------------------------------------------------------------------ > To unsubscribe from si-list: > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field > > or to administer your membership from a web page, go to: > //www.freelists.org/webpage/si-list > > For help: > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field > > > List technical documents are available at: > http://www.si-list.net > > List archives are viewable at: > //www.freelists.org/archives/si-list > or at our remote archives: > http://groups.yahoo.com/group/si-list/messages > Old (prior to June 6, 2001) list archives are viewable at: > http://www.qsl.net/wb6tpu > > > -- ________________________________________ Sol Tatlow, M. Eng. (Oxon) Product Developer Pro Design Electronic GmbH Albert-Mayer-Str. 16 D-83052 Bruckmuehl Phone: +49 (0) 8062/808-302 PCFax: +49 (0) 8062/808-2302 sol.tatlow@xxxxxxxxxxxxxxxxxxxx www.prodesign-europe.com ________________________________________ Vertretungsberechtigte Geschaeftsfuehrer: Helmut Mahr, Ulrike Angersbach, Stephan Roeslmair, Dieter Lessenich Registergericht: Amtsgericht Traunstein Registernummer: HRB 13 002 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu