[SI-LIST] Re: LA probes
- From: "PRAJIT S NAIR" <prajitsnair@xxxxxxxxx>
- To: "steve weir" <weirsi@xxxxxxxxxx>
- Date: Mon, 30 Jul 2007 17:09:22 +0900
Dear Anand,
Actual Voltage: 3.3 Volt
Measured : 2V
*Difference :* 1.3 Volt
Some portion of this difference can come from ground bounce also. So please
check whether you have any simultaneous activities taking place on the board
when you are measuring this voltage? And also check the ground
recommendation for your LA in the user manual..
With Warm Wishes
Prajit
On 7/30/07, steve weir <weirsi@xxxxxxxxxx> wrote:
>
> Anand, if a static logic high level is getting dragged down, then you
> have some fundamental problem like a terminator enabled in the probe or
> perhaps the FPGA input buffer that you do not intend or even a trace
> short. First find out if this is due to the LA or not. If the problem
> appears only with the LA connected then check your manuals to insure you
> have: a correctly selected and functioning probe head, that is set-up
> properly. If the problem appears without the LA connected, then you
> likely have:
>
> * Misprogrammed FPGA that has terminators enabled within the FPGA I/O
> cells
> * Bus contention
> * A wiring problem
>
> Steve
>
> SRINIVASAN ANAND-B06739 wrote:
> > I have mapped to CMOS logic family. The probe impedance is 20K. I am
> > seeing a voltage of 2.0 V on a static pin on which I was expecting 3.3V.
> >
> >
> > -----Original Message-----
> > From: olaney@xxxxxxxx [mailto:olaney@xxxxxxxx]=20
> > Sent: Monday, July 30, 2007 12:00 PM
> > To: prajitsnair@xxxxxxxxx
> > Cc: SRINIVASAN ANAND-B06739; si-list@xxxxxxxxxxxxx
> > Subject: Re: [SI-LIST] Re: LA probes
> >
> > Does the logic analyzer allow you to specify the logic family
> > parameters?
> > You might have the wrong setting, for instance PECL loading on a CMOS
> > signal.
> >
> > Orin
> >
> > On Mon, 30 Jul 2007 15:19:39 +0900 "PRAJIT S NAIR"
> > <prajitsnair@xxxxxxxxx> writes:
> >
> >> Dear Anand
> >> It may be happening because of probe loading. Please check your
> Probe=20
> >> Capacitance, Frequency of Operation and also Load impedance.
> >> =20
> >> =20
> >> Best Regards
> >> Prajit
> >> =20
> >> =20
> >> On 7/30/07, SRINIVASAN ANAND-B06739 <anand.srinivasan@xxxxxxxxxxxxx>
> >> wrote:
> >>
> >>> Content-Type: text/plain;
> >>> charset=3D"us-ascii"
> >>> Content-Transfer-Encoding: quoted-printable Hi All, I have a=20
> >>> problem. Given below is a topology that i have.=3D20
> >>>
> >>>
> >>>
> >>> =3D20
> >>>
> >>> =3D20
> >>>
> >>> I have a bidirectional bus which connects a FPGA to the CHIP. The=20
> >>> distance between them is 2 inches. Now to probe this bus, i have
> >>>
> >> the
> >>
> >>> signals coming out to the right at a distance of about 6 inches.=20
> >>>
> >> Note
> >>
> >>> that i am using active probes to probe this interface and there
> >>>
> >> are NO
> >>
> >>> buffers on the line between the chip and LA probes. Now the
> >>>
> >> problem is
> >>
> >>> that when the LA is plugged in I find that the strength of the
> >>>
> >> signals
> >>
> >>> driven by the chip comes down from 3.3V to 2V. Without the LA
> >>>
> >> plugged,
> >>
> >>> the signal strength remains intact. Could anyone help me in=20
> >>> understanding this? If a solution is possible to get around this,
> >>>
> >> it
> >>
> >>> will be great.
> >>>
> >>> =3D20
> >>> Regards,
> >>> Anand
> >>>
> >>> =3D20
> >>>
> >>> =3D20
> >>>
> >>>
> >>>
> >>>
> >>> -- Binary/unsupported file stripped by Ecartis --
> >>> -- Type: image/jpeg
> >>> -- File: Outlook.jpg
> >>> -- Desc: Outlook.jpg
> >>>
> >>>
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> Steve Weir
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