[SI-LIST] Re: Job Opportunities
- From: "jeremy hillcrest" <jhc_1@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 04 Sep 2003 17:15:08 -0400
Hi All,
I was called on these jobs today and he had asked if I would post them to
the list. Since I've seen a couple of postings on here lately of people
looking for jobs, I thought it appropriate. Please contact Charles directly.
Here is his contact information. The postings are below.
Charles Keegan
A.C.I.
p. 781-932-3750 ext. 206
f. 781-932-4772
cdk@xxxxxxxxxxxxxxxxxxxxxxxx
www.employmentconsulting.com
1) Research and Development Engineer, Signal Integrity
Responsibilities:
Participate as an R & D team member in the research and development of state
of the art full wave and quasistatic electromagnetic field solvers based on
integral and/ or differential equation formulations.
Develop new features and algorithms for existing signal integrity products.
Participate in defining requirements and specifications for new signal
integrity products.
Requirements:
MS or Ph.D. in Engineering, Physics, or Applied Mathematics with
specialization in computational electromagentics.
Good software engineering skills.
Strong knowledge of C, C++ and object oriented design.
Familiarity with UNIX and Windows software development environments.
Ability to quickly assimilate code and leverage new development using
existing libraries.
Excellent self-motivation and independent problem solving skills.
Ability to communicate effectively in conversation, presentations, and
written documents.
Strong attention to detail and pride in one's work.
2) Research and Development Engineer, High Frequency
Responsibilities:
Participate as an R & D team member in the development of state-of-the-art
full-wave simulation solvers.
Develop new features and modeling algorithms for existing and new products.
Participate in defining new requirements and specifications of new products.
Requirements:
MS or Ph.D. in Engineering, with specialization in high frequency
electromagnetics.
Good knowledge of data structure and algorithm design.
Familiarity with UNIX and Windows based development systems.
Strong knowledge of C/C++ and object-oriented design techniques.
Ability to assimilate code quickly and leverage new code off existing
libraries.
Good problem-solving skills, self-confidence, self-motivation, and pride in
one's work.
Strong attention to detail.
3) Compiler Engineer:
The successful candidate will be responsible for developing and maintaining
code, particularly compilers and converters, for their system simulation
tools. It will be necessary to expand existing compilers with new language
constructs as well as develop the compilers necessary to support different
HDL's like Verilog-A and VHDL-AMS.
Qualified candidates should possess the following:
MS in Computer Science.
Excellent software engineering skills, with experience in C/C++ and
object-oriented design.
Strong knowledge of compiler tools, like Yacc, Lex, PCCT or ANTLR.
Knowledge about HDL's (VHDL, MAST or VHDL-AMS).
Ability to quickly assimilate code and leverage new development.
Excellent self-motivation and independent problem solving skills.
Strong attention to detail and pride in one's work.
4) Electromechanical Systems:
The successful candidate will participate as an R & D team member in the
solver development group for their electromechanical system simulators. Be
responsible for designing, developing, and maintaining new features and
modeling algorithms for existing and new EM products.
Qualified candidates should possess the following:
MS or Ph.D. in Computer Science or Electrical Engineering, with strong
knowledge in numerical mathematics and algorithms, circuit solvers and
physics.
3+ years software development experience in C or C++ on Windows NT.
Knowledge of circuit solver technology is required.
Extensive knowledge of MFC and COM is highly desirable.
Familiarity with other numerical solvers in system simulation is a plus.
Ability to assimilate code quickly and leverage new code off existing
libraries.
Good problem-solving skills, self-confidence, self-motivation, and pride in
one's work.
5) Semiconductor Model Developer:
Development group for their Electromechanical system simulation products. Be
specifically responsible for model development in semiconductor and power
electronics. Qualified candidates should possess the following:
MS or PhD in Electrical Engineering, with an excellent understanding of
physics.
Strong knowledge of Semiconductors and Power Electronics.
3+ years of experience in modeling and/or parameterization.
Working knowledge of C/C++ as well as experience with one or more circuit
simulation tools such as Simplorer, Saber, Matlab/ Simulink, or Pspice.
Familiarity with modeling automotive systems is a plusRegards
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>To: si-list@xxxxxxxxxxxxxxx
>Subject: [SI-LIST] Digest Number 824
>Date: 3 Sep 2003 18:52:21 -0000
>
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>There are 8 messages in this issue.
>
>Topics in this digest:
>
> 1. Re: Model of Capacitors
> From: <fred@xxxxxxxxxxxxx>
> 2. ground in RF chip
> From: "Bi, Han" <han.bi@xxxxxxxxx>
> 3. testing LVPECL signal with 50ohm system
> From: "Dan.Zhu" <dan.zhu@xxxxxxxxxx>
> 4. Re: HSpice implementation of recursive convolution
> From: Raymond Anderson <raymond.anderson@xxxxxxx>
> 5. Re: RF ground in RF chip
> From: Bi Han <mike_bihan@xxxxxxxxxxxx>
> 6. Re: HSpice implementation of recursive convolution
> From: "Radoslaw Piesiewicz" <piesiewicz@xxxxxxxxxxxxx>
> 7. Re: RF ground in RF chip
> From: "D G" <dgun@xxxxxxxxxx>
> 8. Re: testing LVPECL signal with 50ohm system
> From: "Bob McNamara" <electronbob@xxxxxxxxxxxxx>
>
>
>________________________________________________________________________
>________________________________________________________________________
>
>Message: 1
> Date: Tue, 2 Sep 2003 09:54:20 -0700 (PDT)
> From: <fred@xxxxxxxxxxxxx>
>Subject: Re: Model of Capacitors
>
> > Hi Fred,
> >
> > I already replied to Zhangkun (directly I believe) on his original post
> > and explained the temp. and voltage dependency of high K-materials.
> > Modeling should be done at the applied voltage.
> >
> > You're refering to X7R or worse class materials when saying +80/-20%
> > tolerance. These type of capacitors are indeed used in decoupling apps
> > etc and typically have large capacitance values (typ. 100nF and above),
> > but are strongly dependent on voltage and temperature.
> > But they offer high capacitance-values, low inductance and (very-)low
> > ESR, so quite suitable for decoupling/filtering. Change in capacitance
> > is not critical here.
> > For resonant circuits however one should never use such X7R ceramic
> > capacitors (also don't forget the piezo effect and the dielectric
> > absorption/memory effect these exhibit).
> >
> > Instead there are NP0/C0G type/class ceramic multilayer capacitors: low
> > values (upto several nF) but very stable against temperature and voltage
> > and showing very low dielectric absorption values.
> > These are used for microwave circuits, such as oscillators, resonance
> > circuits, hi-speed S&H etc. and have tolerances down to 1%.
>
>Bart I totally agree and I am aware of all these effects and even more
>like the effects on teflon, mica, and glass dielectrics. The point I was
>trying to make was the original question is not or should not be relevant
>in modeling because the gross variables mean bypass caps can only be
>treated as minimum values, approximations at best. Kind'a reminds me of my
>students that accquire data with a scope and turn in data with 6 places to
>the right of the decimal point because their calculators have 6 places. A
>waste of good pencil lead.
>
>Fred
>
>
> >
> > best regards, Bart
> >
> >
> >
> >
> >
> >
> > "Fred Townsend" <fred@xxxxxxxxxxxxx>
> >
> > 31-08-03 19:45
> > Sent by: si-list-bounce@xxxxxxxxxxxxx
> >
> > Please respond to fred
> >
> >
> > To: <zhang_kun@xxxxxxxxxx>
> > cc: <si-list@xxxxxxxxxxxxx>
> > Subject: [SI-LIST] Re: Model of Capacitors
> > Category:
> >
> >
> >
> >> Dear all:
> >> I have one question about decoupling effect of caps. When the voltage
> >> on the caps is changing, does the decouling effect of capacitor
> >> change?
> >
> > Simple answer, Yes! Lots!
> >
> > This why anyone using a capacitor value as anything other than a first
> > order approximation is fooling themselves. There are many effects based
> > upon temperature, voltage, history, age, diaelectric, etc.
> >
> > This is also why a bypass type capacitor should never, ever, be used in
> > a critical value circuit (such as resonate circuits).
> >
> > If you have any doubt about the classification of a capacitor take a
> > look at its tolerance. Many bypass caps have a tolerance of +80/-20%!
> >
> > Fred Townsend
> >>
> >> For example, there is one capacitor, 10uF/100V. I measure its model by
> >> means of VNA at low voltage. When the capacitor is used to decouple
> >> -48V, could the model of caps be used?
> >>
> >> Best Regards
> >>
> >> Zhangkun
> >> 2003.08.29
> >>
> >>
> >> ------------------------------------------------------------------ To
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>________________________________________________________________________
>________________________________________________________________________
>
>Message: 2
> Date: Mon, 1 Sep 2003 12:12:44 +0800
> From: "Bi, Han" <han.bi@xxxxxxxxx>
>Subject: ground in RF chip
>
>What¡¯s the question?
>In high speed or RF integrated circuit design, sometimes we need to use
>very long transmission lines in the chip, such as distributed amplifier.
>What we need to in the very first step is to model the transmission line.
>
>For example, we are planning to use CPS(coplanar stripe line) as the
>compensation element in the circuit.
>
>
>
>Issue?
>
>The difficulty was that the ground metal trace in the CPS line will be
>difficult to deal with. We have made experiment to extract the RLGC model
>of the CPS in two ways.
>
>
>
>First, we just made the ground trace as ideal ground.
>
>Second, we model the ground trace as lossy signal line whose two terminals
>was grounded.
>
>
>
>The simulation results showed that the loss of the metal ground will make
>the crosstalk and loss of transmissions greater. This lead to a interesting
>way to improve the performance of CPS in the chip.
>
>We just want to give a better grounding to the CPS¡¯s ground trace, we use
>stacked vias at the outside of ground trace to connect top metal to the
>substrate.
>
>
>
>Do you think that helpful?
>
>
>
>The answer may lead to the questioning where is the acceptable ground in RF
>chip?
>
>
>
>Thanks!
>
>Yours sincerely,
>
>Bi Han
>
>DE/WPS/FPG/Intel Corporation
>
>Phone: 86-(21)-50481818-32283
>
>iNet: 8-753-2283
>
>
>
>
>
>
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>________________________________________________________________________
>________________________________________________________________________
>
>Message: 3
> Date: Tue, 2 Sep 2003 17:25:56 -0400 (EDT)
> From: "Dan.Zhu" <dan.zhu@xxxxxxxxxx>
>Subject: testing LVPECL signal with 50ohm system
>
>Hi,
>
>I have a question on how to test LVPECL signal with 50ohm system like
>digital oscilloscope or Spectrum Analyzer (not
>probeing, just SMA connector on board ->cable-> scope).
>
>Background -
>For the LVPECL(VCC=3.3v & VEE=0v) output, normally a 50ohm termination
>resistor is used between LVPECL output pin and
>a voltage source of Vtt(=VCC-2v) to get a common-mode PECL output level of
>VCC-1.3v. When testing a standalone PECL
>device, people can lower the supply/gnd of pecl device by -2v so VCC'=1.3v,
>VEE'=-2v -> Vtt'=0v, then a digital
>oscilloscope with 50ohm input resistor(to GND) can be used to replace the
>50ohm termination resistor and test the
>signal directly.
>
>Question -
>My question is that if due to some reason, the supply of PECL device can't
>be changed(for example, the pecl device is
>integrated on a mixed-signal IC and change of supply of PECL device is not
>allowed), there is any other way we can
>still test the PECL output signal directly(not probeing, just SMA connector
>on board ->cable-> scope)?
>
>
>Thanks for your suggestion
>
>Best Regards,
>
>Dan Zhu
>
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>
>________________________________________________________________________
>________________________________________________________________________
>
>Message: 4
> Date: Tue, 02 Sep 2003 14:53:28 -0700
> From: Raymond Anderson <raymond.anderson@xxxxxxx>
>Subject: Re: HSpice implementation of recursive convolution
>
>Equations may be evaluated within an Hspice deck at runtime by defining
>the equations within a .param statement.
>
>Here is a snippet from an Hspice deck showing a number of component
>values being calculated by way of equations at runtime:
>
> .param pi2='2*3.14159'
> .param c1=1uF
> .param r1='1/(pi2*fI*c1)'
> .param r2='1/(pi2*z1*c1)'
> .param r3='pi2*z2*r1/(pi2*p1-pi2*z2)'
> .param c2='1/(pi2*z2*(r1+r3))'
> .param c3='1/(pi2*p2*r2)'
>
>I haven't looked into the details of your code, but the general
>implementation might look something like this:
>
>
>.param v = 'Vtran(n1) - Vtran(n2)'
>.param x = 'x+theta*v'
>.param x = 'exp(p_1*dt)*x+ exp(p_1*dt-1)*v'
>.param i_eq = 'k_11*x'
>
>Hopefully this gives you a starting point.
>
>BTW, the 'S element' in the recent versions of Hspice utilizes
>recursive convolution internally when doing time domain simulation
>of s-parameter defined transfer functions.
>
>
>-Ray Anderson
>Sun Microsystems Inc.
>
>
>
>Radoslaw Piesiewicz wrote:
> > Hi,
> > I have a problem, namely how to implement the following code (it is
>recursive convolution) in HSpice, the code is from some simulator that
>works similarly to HSpice. The problem is to calculate the current Curr, it
>is done in two step process
> > at every step in the transient analysis (at the intervals of FIXED
>parameter). The problem is in implementing the part CALC ... ENDCALC
> >
> > Thanks
> >
> > Code:
> >
> > Var k_11 1.0G
> > Var p_1 -5.0G
> > Var dt 2p
> > Var theta FUNC=(p_1**2+exp(p_1*dt))
> > Var x=0
> > Var i_eq 0
> > Var v=0
> >
> > Res 'portVCCS' n1 n2 1.0 G=k_11*theta
> > Curr 'portCurr' n1 n2 TRAN=i_eq
> >
> > Cap 'Cload' n2 GND 1p
> >
> > Volt 'Vin' n1 GND TRAN=1*(t>0)
> >
> > Sweep ''
> > + LOOP 1001 TIME LIN 0 2n FIXED
> > + X 't' 's' 0 2n MULTX='n'
> > + Y 'u_(out)' 'V' 0 2
> >
> > CALC
> >
> > v = Vtran(n1) - Vtran(n2)
> > x= x+theta*v
> > x= exp(p_1*dt)*x+ exp(p_1*dt-1)*v
> > i_eq=k_11*x
> >
> > ENDCALC
> >
> > Show Y Vtran(n2)
> >
> > - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
>- - - - - - - - - - - - - - - -
> > Dipl.-Ing. Radoslaw Piesiewicz
>
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>
>________________________________________________________________________
>________________________________________________________________________
>
>Message: 5
> Date: Wed, 3 Sep 2003 08:18:25 +0800 (CST)
> From: Bi Han <mike_bihan@xxxxxxxxxxxx>
>Subject: Re: RF ground in RF chip
>
>Dear Dan:
>The CPS mentioned in the mail was used in silicon CMOS chip. The ground
>trace was used to lower the loss of signal trace, by attacting the
>eletrical lines from penetrating lossy substrate. CPW was better choice but
>occupies too much space and CPS is the trade off choice.
>
>As I mentioned in last mail, the ground trace was non ideal ground
>reference actually, which will do harm to the performance. Can I tap the
>substrate, which is a very hugh capacitor, to the ground trace, to make it
>better ground?
>
>Han
>"Swanson, Dan" <Dan.Swanson@xxxxxxxxxx> wrote:
>Dear Bi Han
>
>Your problems with CPS are similar to those
>with CPW. "Pure" CPS would have no ground plane
>near by. Adding a local ground plane allows
>additional, unwanted modes. Tieing the CPS ground
>strip to a microstrip groundplane will result
>in a structure that really is not CPS anymore.
>
>If you want pure CPS, a transition to go from
>microstrip to CPS can be found in:
>
>"Coplanar Stripline Resonators Modeling
>and Applications to Filters" Suh and Chang
>MTT Transactions, May 2002, pp 1289-1296.
>
>Dan
>
>Dan Swanson EMAIL: d.swanson@xxxxxxxx
>Andrew Corp. PHONE: 978-834-4085
>37 South Hunt Road FAX: 978-388-7077
>Amesbury, MA 01913
>
>
> > -----Original Message-----
> > From: Bi Han [mailto:mike_bihan@xxxxxxxxxxxx]
> > Sent: Monday, September 01, 2003 12:58 AM
> > To: List` Si
> > Subject: [SI-LIST] RF ground in RF chip
> >
> >
> > What¡¯s the question?
> >
> > In high speed or RF integrated circuit design, sometimes we
> > need to use very long transmission lines in the chip, such as
> > distributed amplifier. What we need to in the very first step
> > is to model the transmission line.
> >
> > For example, we are planning to use CPS(coplanar stripe line)
> > as the compensation element in the circuit.
> >
> >
> >
> > Issue?
> >
> > The difficulty was that the ground metal trace in the CPS
> > line will be difficult to deal with. We have made experiment
> > to extract the RLGC model of the CPS in two ways.
> >
> >
> >
> > First, we just made the ground trace as ideal ground.
> >
> > Second, we model the ground trace as lossy signal line whose
> > two terminals was grounded.
> >
> >
> >
> > The simulation results showed that the loss of the metal
> > ground will make the crosstalk and loss of transmissions
> > greater. This lead to a interesting way to improve the
> > performance of CPS in the chip.
> >
> > We just want to give a better grounding to the CPS¡¯s ground
> > trace, we use stacked vias at the outside of ground trace to
> > connect top metal to the substrate.
> >
> >
> >
> > Do you think that helpful?
> >
> >
> >
> > The answer may lead to the questioning where is the
> > acceptable ground in RF chip?
> >
> >
> >
> > Thanks!
> >
> > Yours sincerely,
> >
> >
> >
> >
> >
> > ---------------------------------
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>________________________________________________________________________
>________________________________________________________________________
>
>Message: 6
> Date: Wed, 3 Sep 2003 11:04:12 +0200
> From: "Radoslaw Piesiewicz" <piesiewicz@xxxxxxxxxxxxx>
>Subject: Re: HSpice implementation of recursive convolution
>
>Thanks for responding,
>
>I have already tried what you suggested. The problem is, that the current
>of
>the source must be updated every, user defined, transient step, here dt.
>This updating is done in a recursive manner in a two step process. I
>enclose
>the listing in HSpice, with suggestions from you, and the problem is that
>the equations seem to be calculated only once and are not updated every dt
>step during transient analysis. How to solve this problem ? (make HSpice
>update given parameters every dt step during transient analysis)
>
>
>.OPTIONS LIST NODE POST
>
>.OP
>
>.PARAM k_11=1g
>
>.PARAM p_1=-5g
>
>.PARAM dt=20p
>
>.PARAM theta='(-1/p_1**2-dt/p_1+exp(p_1*dt)/p_1**2)/dt'
>
>.PARAM x='x+theta*V(1,2)'
>
>.PARAM x='exp(p_1*dt)*x+(exp(p_1*dt)*(p_1*dt-1)+1)*V(1,2)/(dt*p_1**2)'
>
>.PARAM i_eq='k_11*x'
>
>.TRAN dt 2n
>
>V1 1 0 10 AC 1 PWL 1p 0 2p 0.5 4p 1 2n 1
>
>I1 1 2 i_eq
>R1 1 2 1/'k_11*theta'
>
>C1 2 0 1p
>
>
>.END
>-----Ursprüngliche Nachricht-----
>Von: "Raymond Anderson" <raymond.anderson@xxxxxxx>
>An: <piesiewicz@xxxxxxxxxxxxx>
>Cc: "Signal Integrity" <si-list@xxxxxxxxxxxxx>
>Gesendet: Dienstag, 2. September 2003 23:53
>Betreff: Re: [SI-LIST] HSpice implementation of recursive convolution
>
>
> > Equations may be evaluated within an Hspice deck at runtime by defining
> > the equations within a .param statement.
> >
> > Here is a snippet from an Hspice deck showing a number of component
> > values being calculated by way of equations at runtime:
> >
> > .param pi2='2*3.14159'
> > .param c1=1uF
> > .param r1='1/(pi2*fI*c1)'
> > .param r2='1/(pi2*z1*c1)'
> > .param r3='pi2*z2*r1/(pi2*p1-pi2*z2)'
> > .param c2='1/(pi2*z2*(r1+r3))'
> > .param c3='1/(pi2*p2*r2)'
> >
> > I haven't looked into the details of your code, but the general
> > implementation might look something like this:
> >
> >
> > .param v = 'Vtran(n1) - Vtran(n2)'
> > .param x = 'x+theta*v'
> > .param x = 'exp(p_1*dt)*x+ exp(p_1*dt-1)*v'
> > .param i_eq = 'k_11*x'
> >
> > Hopefully this gives you a starting point.
> >
> > BTW, the 'S element' in the recent versions of Hspice utilizes
> > recursive convolution internally when doing time domain simulation
> > of s-parameter defined transfer functions.
> >
> >
> > -Ray Anderson
> > Sun Microsystems Inc.
> >
> >
> >
> > Radoslaw Piesiewicz wrote:
> > > Hi,
> > > I have a problem, namely how to implement the following code (it is
>recursive convolution) in HSpice, the code is from some simulator that
>works
>similarly to HSpice. The problem is to calculate the current Curr, it is
>done in two step process
> > > at every step in the transient analysis (at the intervals of FIXED
>parameter). The problem is in implementing the part CALC ... ENDCALC
> > >
> > > Thanks
> > >
> > > Code:
> > >
> > > Var k_11 1.0G
> > > Var p_1 -5.0G
> > > Var dt 2p
> > > Var theta FUNC=(p_1**2+exp(p_1*dt))
> > > Var x=0
> > > Var i_eq 0
> > > Var v=0
> > >
> > > Res 'portVCCS' n1 n2 1.0 G=k_11*theta
> > > Curr 'portCurr' n1 n2 TRAN=i_eq
> > >
> > > Cap 'Cload' n2 GND 1p
> > >
> > > Volt 'Vin' n1 GND TRAN=1*(t>0)
> > >
> > > Sweep ''
> > > + LOOP 1001 TIME LIN 0 2n FIXED
> > > + X 't' 's' 0 2n MULTX='n'
> > > + Y 'u_(out)' 'V' 0 2
> > >
> > > CALC
> > >
> > > v = Vtran(n1) - Vtran(n2)
> > > x= x+theta*v
> > > x= exp(p_1*dt)*x+ exp(p_1*dt-1)*v
> > > i_eq=k_11*x
> > >
> > > ENDCALC
> > >
> > > Show Y Vtran(n2)
> > >
> >
> > - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
>-
>- - - - - - - - - - - - - - -
> > > Dipl.-Ing. Radoslaw Piesiewicz
> >
> >
>
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>
>
>________________________________________________________________________
>________________________________________________________________________
>
>Message: 7
> Date: Thu, 04 Sep 2003 01:10:04 +0800
> From: "D G" <dgun@xxxxxxxxxx>
>Subject: Re: RF ground in RF chip
>
>Dan,
>
>I haven't had a chance to look at this transition yet, but if it is similar
>to others I have seen, it is band-limited. The title of the paper would
>suggest that this is so. This would prevent its use in most time-domain
>applications since it typically won't work well below 1GHz.
>
>I'll try to track down the paper so I can make a more informed comment, but
>please set me straight if this is not the case.
>
>Daniel
>
>From: "Swanson, Dan" <Dan.Swanson@xxxxxxxxxx>
> > Dear Bi Han
> >
> > Your problems with CPS are similar to those
> > with CPW. "Pure" CPS would have no ground plane
> > near by. Adding a local ground plane allows=20
> > additional, unwanted modes. Tieing the CPS ground
> > strip to a microstrip groundplane will result
> > in a structure that really is not CPS anymore.
> >
> > If you want pure CPS, a transition to go from
> > microstrip to CPS can be found in:
> >
> > "Coplanar Stripline Resonators Modeling
> > and Applications to Filters" Suh and Chang
> > MTT Transactions, May 2002, pp 1289-1296.
> >
> > Dan
> >
> > Dan Swanson EMAIL: d.swanson@xxxxxxxx
> > Andrew Corp. PHONE: 978-834-4085
> > 37 South Hunt Road FAX: 978-388-7077
> > Amesbury, MA 01913
> >
> >
> > > -----Original Message-----
> > > From: Bi Han [mailto:mike_bihan@xxxxxxxxxxxx]
> > > Sent: Monday, September 01, 2003 12:58 AM
> > > To: List` Si
> > > Subject: [SI-LIST] RF ground in RF chip
> > >=20
> > >=20
> > > What=A1=AFs the question?
> > >=20
> > > In high speed or RF integrated circuit design, sometimes we=20
> > > need to use very long transmission lines in the chip, such as=20
> > > distributed amplifier. What we need to in the very first step=20
> > > is to model the transmission line.
> > >=20
> > > For example, we are planning to use CPS(coplanar stripe line)=20
> > > as the compensation element in the circuit.=20
> > >=20
> > > =20
> > >=20
> > > Issue?
> > >=20
> > > The difficulty was that the ground metal trace in the CPS=20
> > > line will be difficult to deal with. We have made experiment=20
> > > to extract the RLGC model of the CPS in two ways.=20
> > >=20
> > > =20
> > >=20
> > > First, we just made the ground trace as ideal ground.=20
> > >=20
> > > Second, we model the ground trace as lossy signal line whose=20
> > > two terminals was grounded.=20
> > >=20
> > > =20
> > >=20
> > > The simulation results showed that the loss of the metal=20
> > > ground will make the crosstalk and loss of transmissions=20
> > > greater. This lead to a interesting way to improve the=20
> > > performance of CPS in the chip.=20
> > >=20
> > > We just want to give a better grounding to the CPS=A1=AFs ground=20
> > > trace, we use stacked vias at the outside of ground trace to=20
> > > connect top metal to the substrate.
> > >=20
> > > =20
> > >=20
> > > Do you think that helpful?=20
> > >=20
> > > =20
> > >=20
> > > The answer may lead to the questioning where is the=20
> > > acceptable ground in RF chip?
> > >=20
> > > =20
> > >=20
> > > Thanks!
> > >=20
> > > Yours sincerely,
>
>--
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>
>Message: 8
> Date: Wed, 3 Sep 2003 06:49:40 -0700
> From: "Bob McNamara" <electronbob@xxxxxxxxxxxxx>
>Subject: Re: testing LVPECL signal with 50ohm system
>
>[Sorry, forgot to copy the reflector the first time]
>
>What I've done in the past is to terminate the signal in
>a Thevenin equivalent to Vcc-2V and use the 50ohm termination
>in the scope as part of the Thevenin circuit.
>
>For example in your case of LVPECL at 3.3V, you could use
>127 Ohms to +3.3V and 83 Ohms to ground. That gives you a
>Thevenin equivalent resistance of 50.2 Ohms and a Thevenin
>voltage of 1.304 Volts. The 83 Ohm resistance consists
>of 33 Ohms on your module and 50 Ohms in the scope.
>Then you set up your scope with an external attenuation
>of 1.66:1 as a result of the voltage divider formed by
>the 33 Ohm resistor and 50 Ohm termination.
>
>Bob
>
>
> > ------------Original Message-------------
> > From: "Dan.Zhu" <dan.zhu@xxxxxxxxxx>
> > To: si-list@xxxxxxxxxxxxx
> > Cc: dan.zhu@xxxxxxxxxx
> > Date: Tue, Sep-2-2003 2:27 PM
> > Subject: [SI-LIST] testing LVPECL signal with 50ohm system
> >
> > Hi,
> >
> > I have a question on how to test LVPECL signal with 50ohm system like
>digital oscilloscope or Spectrum Analyzer (not
> > probeing, just SMA connector on board ->cable-> scope).
> >
> > Background -
> > For the LVPECL(VCC=3.3v & VEE=0v) output, normally a 50ohm termination
>resistor is used between LVPECL output pin and
> > a voltage source of Vtt(=VCC-2v) to get a common-mode PECL output level
>of VCC-1.3v. When testing a standalone PECL
> > device, people can lower the supply/gnd of pecl device by -2v so
>VCC'=1.3v, VEE'=-2v -> Vtt'=0v, then a digital
> > oscilloscope with 50ohm input resistor(to GND) can be used to replace
>the 50ohm termination resistor and test the
> > signal directly.
> >
> > Question -
> > My question is that if due to some reason, the supply of PECL device
>can't be changed(for example, the pecl device is
> > integrated on a mixed-signal IC and change of supply of PECL device is
>not allowed), there is any other way we can
> > still test the PECL output signal directly(not probeing, just SMA
>connector on board ->cable-> scope)?
> >
> >
> > Thanks for your suggestion
> >
> > Best Regards,
> >
> > Dan Zhu
> >
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> >
> >
> >
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