[SI-LIST] Job Openings at Altera

  • From: "Larry Smith" <LSMITH@xxxxxxxxxx>
  • To: "silist" <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 12 Oct 2006 11:15:29 -0700

Altera has a few openings in our packaging group.  Please correspond
directly with Jeff Aksamit.
 

JAKSAMIT@xxxxxxxxxx

 

Regards,

Larry Smith

Altera Corporation

 

 
________________________________________________________________________
_________

Title: Package Electrical Design Engineer, MTS

Location: US-CA-San Jose

Responsibilities: 

As a Design Engineer, MTS, you will be a part of the package development
team in supporting electrical design of packages to meet product
development and characterization objectives. You will work closely with
new product design and rollout teams and provide representative package
models to facilitate compliance to desired specifications in a timely
manner. You will work with EDA tool vendors to enhance package modeling
methodologies and capabilities.

The successful candidate's qualifications will include the following:

*       BS in EE or Engineering or equivalent 
*       5 years direct experience in electrical simulation of packages
and associated system level simulations in HSPICE/ADS environments 
*       familiar with HFSS, Power SI and Ansoft tools 
*       hands on experience in associated electrical characterization
methodologies involving VNA measurements and analysis 
*       strong written and verbal communication skills 

________________________________________________________________________
________________ 

 

Title: Package Design Engineer, Senior MTS

Location: US-CA-San Jose

Responsibilities: 

As a Senior MTS, Package Design Engineer, you will work on advanced IC
package design methodology development and new product package solution
development. You will work with internal engineering team including IC
Design, Marketing and Product Engineering to develop next generation
package design strategy and guideline.  This will include conducting
performance, cost and DFM trade off analysis, working with external
substrate vendors and assembly subcontractors to ensure the most cost
effective packaging solutions being applied and high quality package
design that added marketing value to the company's future product.

The successful candidate's qualifications will include the following:

*       MSEE or equivalent 
*       5 years of advanced IC packaging design engineering experience 
*       familiar with silicon-package -PCB system co-design concept and
associated signal integrity consideration 
*       familiar with advanced packaging technology and key players in
the world 
*       hands-on package design engineering experience 
*       good communication and leadership skills 

 

 

Title:  Package Design Engineer, MTS

Location: US-CA-San Jose

Responsibilities: 

As a Design Engineer, MTS, you will be the primary packaging interface
with development teams. You will be responsible for generating
appropriate models in a timely manner to be used for developing SSN
tools. Also, you will be responsible for developing and implementing
infrastructure for deployment and dissemination of packaging information
- models, data and technologies that meets corporate standards

The successful candidate's qualifications will include the following:

*       BSEE or equivalent 
*       5 years relevant experience in an IC-EDA environment 
*       familiar with IC and packaging industry 
*       excellent written communication skills 

 


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