## [SI-LIST] Re: Jitter transfer vs. accumulation

• From: "Tang, George" <George.Tang@xxxxxxx>
• To: <Chris.Cheng@xxxxxxxxxxxx>, <Istvan.Novak@xxxxxxx>
• Date: Fri, 23 Mar 2007 20:27:37 -0600

```Chris,=20

When a customer asks the question, they are interested in getting their
system to work flawlessly, so we love to help answer their questions.
When you ask the question, you are looking for ways to break the chip.
Especially when you say "I once did a frequency sweep on your company's
PLL and it blew up."  We did not observe the event, we did not know
under what operating condition or the noise environment, we did not know
what other destructive tests you did on the chip before hand, so we have
absolutely no way to defend against such hear-say.  Now what do you
expect? =20

=20
=20
George=20
=20

Note: Effective October 14, 2006, My LSI Logic Email address will change
to: george.tang@xxxxxxx

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Chris Cheng
Sent: Friday, March 23, 2007 2:02 PM
To: Tang, George; Istvan.Novak@xxxxxxx
Cc: Alfred P. Neves; weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Jitter transfer vs. accumulation

"I know you have a hard time understanding the fact that the test you =
=3D
are describing is not a valid test, and the zero-phase-margin-phenomenon
=3D
occurs only when you drive the power noise with too large an amplitude =
=3D
because you are controlling the gain of the input with your noise =3D
amplitude.  Your noise modulates the VCO directly and completely =3D
by-passed the phase comparator input all together.  The gain limitation
=3D
of the phase comparator is taken out of the loop.  This has everything =
=3D
to do with the phase margin of the resulting circuit that you have =3D
created.  But you have a hard time understanding that.  Most newer PLL =
=3D
designs now have on-chip voltage regulator to filter and minimize the =
=3D
effects of power noise.  But no voltage regulator will survive the type
=3D
of destructive tests that you do.  These tests do not happen with normal
=3D
operation.  I know you want a BMW that will survive a nuclear blast =3D
because you think BMWs have a lot of sheet metals on the outside.  But I
=3D
am sure that you will not be willing to pay for the price when they make
=3D
such a car for you.  Enough of these senseless arguing."

Didn't I ask you exactly the same thing and you answered with the above
=3D
reply ? What does the vdd noise power spec has anything to do with zero
=3D
phase margin again ? Are you trying to dance your way out now ?

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Tang, George
Sent: Friday, March 23, 2007 1:00 PM
To: Istvan.Novak@xxxxxxx
Cc: Alfred P. Neves; weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Jitter transfer vs. accumulation

Well, the +/- 5% is the generic spec.  Depending on what applications
you are interested in, say OIF 6G, or XAUI, or GPON, etc, all having
different jitter specs, your power spec will be different for different
applications.  There is no point in making everyone to meet the toughest
specs when his application does not require it.  We can (and do)
characterize to your specific application with a certain power noise
tolerance to demonstrate the chip performance and give you the
confidence level you require. =3D3D20

Thanks,=3D3D20
=3D3D20
George=3D3D20
=3D3D20

Note: Effective October 14, 2006, My LSI Logic Email address will change
to: george.tang@xxxxxxx

-----Original Message-----
From: Istvan.Novak@xxxxxxx [mailto:Istvan.Novak@xxxxxxx]=3D3D20
Sent: Friday, March 23, 2007 12:34 PM
To: Tang, George
Cc: Alfred P. Neves; weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Jitter transfer vs. accumulation

Hello George,

Thanks.  Let me see if I understand what this means.  Does this mean
that with up to +/- 5...10% periodic distrurbance of any frequency on
any of the analog pins of the chip, the jitter will not go beyond the
specified limit (whatever number it is)?

Regards,
Istvan Novak

Tang, George wrote On 03/23/07 14:53,:
> Hello Istvan,=3D3D20
>=3D3D20
> Yes, we have a specification of VDD +/- 5%, but the chips are designed
> and simulated to VDD +/- 10%, just to give ourselves (and the
customers)
> some margin. =3D3D20
>=3D3D20
> Thanks,=3D3D20
> =3D3D20
> George=3D3D20
> =3D3D20
>=3D3D20
> Note: Effective October 14, 2006, My LSI Logic Email address will
change
> to: george.tang@xxxxxxx
>=3D3D20
>=3D3D20
>=3D3D20
> -----Original Message-----
> From: Istvan.Novak@xxxxxxx [mailto:Istvan.Novak@xxxxxxx]=3D3D20
> Sent: Friday, March 23, 2007 4:46 AM
> To: Tang, George
> Cc: Alfred P. Neves; weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Re: Jitter transfer vs. accumulation
>=3D3D20
> George,
>=3D3D20
> I have been following with great interest the discussion on =3D
jitter.=3D3D20
> I need to admit that I did my PhD on stochastic processes in
> precision measurements many years ago, so my math has become
> rusty.  For this reason I will leave the details to those who practice
> them today.=3D3D20
>=3D3D20
> However, I have a question to you about the applications.  If I am
> not mistaken, in your arguments you assume that the power going
> to the VCO and PLL circuit is clean, or at least clean enough that
> power-supply modulation can be neglected.  Does this mean that
> for chips that you design the customers get a specification regarding
> how clean the supply rail needs to be going to the analog pins?
>=3D3D20
> Regards,
>=3D3D20
> Istvan Novak
> SUN Microsystems
>=3D3D20
>=3D3D20
> Tang, George wrote:
>=3D3D20
>=3D3D20
>>Alfred,=3D3D3D20
>>
>>See comments in [[[[[ ]]]]]. =3D3D3D20
>>
>>George=3D3D3D20
>>
>>
>>-----Original Message-----
>>From: Alfred P. Neves [mailto:al.neves@xxxxxxxxxxx]=3D3D3D20
>>Sent: Wednesday, March 21, 2007 11:07 PM
>>To: weirsi@xxxxxxxxxx; Tang, George; si-list@xxxxxxxxxxxxx
>>Subject: RE: [SI-LIST] Re: Jitter transfer vs. accumulation
>>
>>George,
>>
>>
>>=3D3D20
>>
>>
>>>{{{{{Alfred made the initial postulate that open-loop VCO has =3D3D
rms=3D3D3D20
>>>jitter governed by his funny equation Y=3D3D3D3DmX + b, where Y is =
the
>=3D3D20
> rms=3D3D3D20
>=3D3D20
>>>jitter, X is the time duration of measurement, and m > 0.  This
>=3D3D20
> shows=3D3D3D20
>=3D3D20
>>>that as time goes to infinity, the rms jitter of the open-loop VCO
>=3D3D20
> also
>=3D3D20
>>>  =3D3D20
>>>
>>
>>=3D3D20
>>
>>
>>>goes to infinity.
>>>  =3D3D20
>>>
>>
>>No George, this is not what I said.  It is the autocorrelation record
>=3D3D20
> of
>=3D3D20
>>the VCO that increases linearly on a log-log plot, where the axis are
>>log(RMS jitter) and log(time interval length), where this is not to be
>>confused with an RMS jitter or whether it is bounded or not. =3D3D3D20
>>
>>[[[[[Amazing.  If your autocorrelation record for the open-loop VCO
>>looks like Y=3D3D3D3DmX + b, you have either invented a =3D
random-noise-free
>=3D3D20
> that
>=3D3D20
>>it is completely dominated by deterministic modulation so you cannot
>>take clean measurements at all.  My guess is that the latter case is
>=3D3D20
> the
>=3D3D20
>>truth.  ]]]]]]]=3D3D3D20
>>
>>
>>provided numerous references regarding this and can also provide
>>numerous measurements for several VCO's to illustrate VCO RMS jitter
>>characteristics versus measurement interval.  We have used this
>=3D3D20
> analysis
>=3D3D20
>>100's of times for closed (and open loop) PLL analysis to determine
the
>>PLL loop bandwidth and peaking in the PLL loop response. =3D3D3D20
>>
>>[[[[[Like I said before, we do not see this problem in our
>=3D3D20
> measurements.
>=3D3D20
>>The VCO RMS jitter is bounded, and so is the PLL RMS jitter.  The RJ
>>distribution takes on a true Gaussian waveform.  In addition to that,
>=3D3D20
> we
>=3D3D20
>>test our communication channels (including TX, RX, &PLL) for weeks
with
>>no errors.  All our measurements fairly closely match up with the
>=3D3D20
> system
>=3D3D20
>>BER predicted by the model simulation.  We do not see the problems
that
>>you are fighting with.  ]]]]]=3D3D3D20
>>
>>
>>You can also
>>use this analysis to analyze jitter problems like spurious response
due
>>to charge pump leakage, power supply junk like switching noise or HF
>>digital, XTALK in the substrate, SSO, and jitter multiplication from
>=3D3D20
> PLL
>=3D3D20
>>to PLL.  The basis for this analysis is work by John McNeil in
>>collaboration with Analog Devices in the mid 90's - have you read the
>>reference already provided, I can send you a copy if need be?   I
>=3D3D20
> didn't
>=3D3D20
>>originate the concept, just use the practical elements to analyze
PLL's
>>and VCO's.  Before you belittle this, become dismissive, or make any
>>more personally targeted comments it may behoove you to do a bit of
>>homework.   And once again, you are asked to significantly raise the
>>
>>=3D3D20
>>
>>
>>>He further claimed that with the feedback loop of=3D3D3D20
>>>the PLL, the rms jitter became bounded.  You don't think Alfred
was=3D3D3D20
>>>crazy enough to make the mistake of comparing phase jitter of VCO
>=3D3D20
> to=3D3D3D20
>=3D3D20
>>>the RMS jitter of the PLL, do you?  That will be comparing apples
>=3D3D20
> to=3D3D3D20
>=3D3D20
>>>bananas, let alone oranges
>>>  =3D3D20
>>>
>>
>>No, I did not say this either.  The reference was regarding the
>>autocorrelation record, NOT any comment regarding characteristics of
>=3D3D20
> VCO
>=3D3D20
>>RMS jitter.  A VCO has certain properties:   It has poor frequency
>>stability, it is temperature sensitive, it is not WSS (wide sense
>>stationary), it has a LOT of low frequency jitter due to numerous 1/f
>>noise sources, it also has unbounded RMS jitter, but the estimate of
>=3D3D20
> the
>=3D3D20
>>RMS jitter is difficult to measure since:   Measure the RMS of a VCO
>>over a certain time T, remeasure the RMS jitter later over the same
>=3D3D20
> time
>=3D3D20
>>interval and you will arrive at a different RMS number since it is not
>=3D3D20
> a
>=3D3D20
>>stationary process.   Sample size really has little to do with this.
>>BTW, do you have data on "stable" VCO's in terms of PPM frequency
drift
>>versus time, after you claim the temperature stabilizes in 1-2 hours.
>>
>>[[[[[If the RMS RJ of the VCO is unbounded, the closed-loop PLL will
>>never be fully stable since the feedback has finite correction
>>capability.  The only way the PLL can be fully stable is that the RMS
>>jitter of the VCO HAS TO BE BOUNDED.  We measure the PLL for say 20
>>minutes on day one and another 20 minutes on day 2 and day 3, and the
>>Peak-to-Peak jitter and RMS jitter for each day matches the results of
>>the other days down to 0.1ps range.  To say that the VCO and/or the
PLL
>>has unbounded RMS jitter will be a tough tough sell, since you will
>>never be able to get this kind of repeatability otherwise.  =3D3D
]]]]]]=3D3D3D20
>>
>>
>>NOW, place the VCO into a PLL loop that is locked on a stable input
>>signal, the VCO accumulated phase jitter  is shaped by the PLL loop
>>response.  The RMS RJ jitter measured (using some RJ-DJ extraction)
>=3D3D20
> will
>=3D3D20
>>be unbounded  - by definition.   =3D3D3D20
>>
>>[[[[[Why?  What equipment do you use to give you such results? ]]]]]
>>
>>The resulting PLL accumulated jitter,
>>phase jitter, or autocorrelation record will not continue to increase
>>past a value related to the PLL loops bandwidth, however (assuming the
>>loop is stable).  =3D3D3D20
>>
>>
>>[[[[[Phase jitter is bounded??  What equipment shows that! ]]]]]]
>>
>>This is due to the intrinsic PLL loop gain. =3D3D3D20
>>
>>[[[[[No, you are wrong, again.  Even when the PLL is in the locked
>>operation, the feedback can only correct the VCO jitter within the
loop
>>bandwidth.  Beyond that, the feedback cannot do anything, period.
When
>>the overall PLL output RMS jitter is measured to be bounded across all
>>frequencies, then the VCO RMS jitter *must also be bounded across all
>>frequencies*. =3D3D3D20
>>
>>On the other hand, phase jitter for a locked PLL is unbounded due to
>>probability of random events.  ]]]]]
>>
>>
>>My point is that the way to deal with both VCO's and the VCO-PLL
>>integrated loop is with autocorrelation analysis.  We have addressed a
>>lot of data recovery issues, PLL and VCO design issues using these
>>methods, solved a lot of problems.   Unfortunately, these methods are
>>not used that heavily (there is one exception in the industry
however),
>>but we see value in the approach especially in regard to Chris's
>=3D3D20
> initial
>=3D3D20
>>email where you want to analyze peaking and jitter multiplication from
>>TX to RX, including models of the reference PLL or oscillator and
>=3D3D20
> signal
>=3D3D20
>>path.
>>
>>[[[[[I do not doubt the validity of autocorrelation theories, but I
>>highly suspect that you have valid data to support your claims.
>>Especially when your environment gives you data in the form of Y =3D
=3D3D3D3D
mX
>=3D3D20
> =3D3D3D
>=3D3D20
>>+
>>b.  ]]]]]
>>
>>
>>
>>Alfred P. Neves      <*)))))><{
>>
>>=3D3D3D20
>>Hillsboro Office:
>>735 SE 16th Ave.
>>Hillsboro, OR, 97123
>>(503) 679 2429 Voice
>>(503) 210 7727 Fax
>>=3D3D3D20
>>Main Corporate office:
>>Teraspeed Consulting Group LLC=3D3D3D20
>>121 North River Drive=3D3D3D20
>>Narragansett, RI 02882
>>(401) 284-1840 Fax=3D3D3D20
>>http://www.teraspeed.com
>>=3D3D3D20
>>Teraspeed is the registered service mark=3D3D3D20
>>of Teraspeed Consulting Group LLC
>>=3D3D3D20
>>
>>
>>-----Original Message-----
>>From: si-list-bounce@xxxxxxxxxxxxx
>=3D3D20
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>=3D3D20
>>On Behalf Of steve weir
>>Sent: Wednesday, March 21, 2007 8:29 PM
>>To: Tang, George; si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Re: Jitter transfer vs. accumulation
>>
>>
>>At 05:02 PM 3/21/2007, you wrote:
>>=3D3D20
>>
>>
>>>Steve,
>>>
>>>
>>>
>>>George
>>>
>>>
>>>snip
>>>-----Original Message-----
>>>From: steve weir [mailto:weirsi@xxxxxxxxxx]=3D3D3D3D20
>>>Sent: Tuesday, March 20, 2007 4:10 AM
>>>To: Tang, George; Alfred P. Neves; Chris Cheng; si-list@xxxxxxxxxxxxx
>>>Subject: Re: [SI-LIST] Re: Jitter transfer vs. accumulation
>>>
>>>George, please correct me if I am wrong, but I believe:
>>>
>>>1) That the inverter gain K is both temperature and supply =3D3D
voltage=3D3D3D20
>>>dependent.
>>>
>>>{{{{{True, not a function of time. }}}}}
>>>
>>>  =3D3D20
>>>
>>
>>Good.  Then do we also agree that when the supply voltage and=3D3D3D20
>>temperature both vary with time that the gain does as well?  If not
>=3D3D20
> why?
>=3D3D20
>>
>>=3D3D20
>>
>>
>>>2) That even in an isothermal, constant supply, and zero noise =
=3D3D3D
>>>  =3D3D20
>>>
>>
>>Vref=3D3D3D3D20=3D3D3D20
>>=3D3D20
>>
>>
>>>environment, running open-loop that in the limit any single
>=3D3D20
> VCO=3D3D3D3D20=3D3D3D20
>=3D3D20
>>>output interval can vary from epsilon*ring_stages to
>=3D3D20
> approximately=3D3D3D3D20 =3D3D3D
>=3D3D20
>>>  =3D3D20
>>>
>>
>>=3D3D20
>>
>>
>>>Vcc/Vths_nom*UI*ring_stages.
>>>
>>>{{{{{You CANNOT rewrite the laws of physics with your funny
>=3D3D20
> formula.=3D3D3D20
>=3D3D20
>>>The input sensitivity (in mV) is not proportional to VCC voltage
>=3D3D20
> nor=3D3D3D20
>=3D3D20
>>>inversely proportional to Vth.  Throwing such formulae around does
>=3D3D20
> not=3D3D3D20
>=3D3D20
>>>fool people into believing you.  }}}}}
>>>  =3D3D20
>>>
>>
>>George there is no attempt to "fool people".  Please keep the=3D3D3D20
>>discussion on a professional level.
>>
>>The minimum period for one inverter in the presence of a large
>=3D3D20
> enough=3D3D3D20
>=3D3D20
>>shot noise pulse is the inverter minimum delay time epsilon, is it
not?
>>An arbitrarily large noise shot pulse can only defer a transition
by=3D3D3D20
>>a maximum amount of time.  If you object to the approximation =3D
of=3D3D3D20
>>Vcc/Vths I am open to discussion of alternative approximations.
>>
>>
>>=3D3D20
>>
>>
>>>Maybe I don't understand what you mean by
>>>
>>>"My assertion is that when temperature,
>>>voltage, low noise level and fixed noise frequency parameters are
>=3D3D20
> all=3D3D3D20
>=3D3D20
>>>in steady-state condition, the open-loop VCO output jitter shall
be=3D3D3D20
>>>constant."
>>>
>>>{{{{{The output RMS jitter shall be constant.  When we talk about
>=3D3D20
> PLL=3D3D3D20
>=3D3D20
>>>or VCO jitter, we usually talk about the RMS jitter.  Phase jitter
>=3D3D20
> is=3D3D3D20
>=3D3D20
>>>meaningless unless you specify the sample size.  }}}}}
>>>
>>>
>>>That sounds like Dj induced from power supply feedback.
>>>
>>>
>>>{{{{{Whatever the cause, the result is the same.  }}}}}
>>>  =3D3D20
>>>
>>
>>OK I think we agree there is a big difference between peak jitter
>=3D3D20
> and=3D3D3D20
>=3D3D20
>>RMS jitter.  So, I think we can put that aside and concentrate on RMS
>>jitter.
>>
>>
>>=3D3D20
>>
>>
>>>My interpretation is that even in this pristine environment of
>=3D3D20
> a=3D3D3D3D20=3D3D3D20
>=3D3D20
>>>perfect power supply the oscillator exhibits unbounded Rj.  If it =3D
=3D3D3D
>>>  =3D3D20
>>>
>>
>>is=3D3D3D3D20
>>
>>=3D3D20
>>
>>
>>>bounded, what limits it?
>>>
>>>{{{{{Alfred made the initial postulate that open-loop VCO has =3D3D
rms=3D3D3D20
>>>jitter governed by his funny equation Y=3D3D3D3DmX + b, where Y is =
the
>=3D3D20
> rms=3D3D3D20
>=3D3D20
>>>jitter, X is the time duration of measurement, and m > 0.  This
>=3D3D20
> shows=3D3D3D20
>=3D3D20
>>>that as time goes to infinity, the rms jitter of the open-loop VCO
>=3D3D20
> also
>=3D3D20
>>>  =3D3D20
>>>
>>
>>=3D3D20
>>
>>
>>>goes to infinity.  He further claimed that with the feedback loop
>=3D3D20
> of=3D3D3D20
>=3D3D20
>>>the PLL, the rms jitter became bounded.  You don't think Alfred
was=3D3D3D20
>>>crazy enough to make the mistake of comparing phase jitter of VCO
>=3D3D20
> to=3D3D3D20
>=3D3D20
>>>the RMS jitter of the PLL, do you?  That will be comparing apples
>=3D3D20
> to=3D3D3D20
>=3D3D20
>>>bananas, let alone oranges.
>>>
>>>My claim is that both VCO rms jitter and PLL rms jitter are
>=3D3D20
> bounded,=3D3D3D20
>=3D3D20
>>>and the closed-loop feedback circuit simply attenuates the
>=3D3D20
> open-loop=3D3D3D20
>=3D3D20
>>>rms jitter.  Both circuits have unbounded phase jitters.  }}}}}
>>>  =3D3D20
>>>
>>
>>So it sounds to me that we agree that Rj is unbounded.  My
>=3D3D20
> experience=3D3D3D20
>=3D3D20
>>agrees with Al's assertion that due to Rj, RMS jitter does =3D
creep=3D3D3D20
>>upwards with time.  This is the evil of the 1/f noise corner=3D3D3D20
>>exhibited by every DC amplifier I have encountered.  If noise
>=3D3D20
> density=3D3D3D20
>=3D3D20
>>/ square root frequency were the RMS value wouldn't creep.  What is
>>wrong here?
>>
>>I have to agree with you that an indefinite divided by a definite
is=3D3D3D20
>>still indefinite.  Al will have to address whether he was saying
>=3D3D20
> that=3D3D3D20
>=3D3D20
>>feedback bounds peak jitter, and if so why.
>>
>>
>>
>>=3D3D20
>>
>>
>>>In my world, ( which may be perverse ) the only way that we get
>=3D3D20
> to=3D3D3D3D20 =3D3D3D
>=3D3D20
>>>  =3D3D20
>>>
>>
>>=3D3D20
>>
>>
>>>bound Rj is to bound the number of UIs, and we don't get to do =
=3D3D3D
>>>  =3D3D20
>>>
>>
>>that=3D3D3D3D20=3D3D3D20
>>=3D3D20
>>
>>
>>>until we close the feedback loop.
>>>
>>>
>>>{{{{{Sorry, another funny theory of yours.  RJ is a =3D
statistical=3D3D3D20
>>>probability.  Bounding the number of UIs does not bound the=3D3D3D20
>>>peak-to-peak RJ.  Closing the feedback loop does not bound RJ p-p.
=3D3D3D20
>>>}}}}}
>>>
>>>  =3D3D20
>>>
>>
>>I acknowledged that I mispoke on this in my private e-mail to=3D3D3D20
>>you.  The likelihood that an event outside some magnitude will
occur=3D3D3D20
>>shrinks with reduced exposure.  Applying feedback cannot reduce =3D3D
the=3D3D3D20
>>limit which remains indefinite.  It does however effectively reduce
>>sigma.
>>
>>=3D3D20
>>
>>
>>>In my mind this goes back to=3D3D3D3D20
>>>Chris' issue which is that from the loop cut-off up to 1/UI the =
=3D3D3D
>>>  =3D3D20
>>>
>>
>>VCO=3D3D3D3D20=3D3D3D20
>>=3D3D20
>>
>>
>>>accumulates phase error based on thermal, power supply noise,
>=3D3D20
> and=3D3D3D3D20=3D3D3D20
>=3D3D20
>>>reference voltage noise disturbances with little or no=3D3D3D3D20 =
=3D3D3D
>>>  =3D3D20
>>>
>>
>>attenuation.
>>
>>=3D3D20
>>
>>
>>>It is only well within the closed loop B/W that=3D3D3D3D20 feedback =
=3D
=3D3D3D
>>>  =3D3D20
>>>
>>
>>diminishes=3D3D3D20
>>=3D3D20
>>
>>
>>>those error terms WRT the apparent reference=3D3D3D3D20 timing =
source.
=3D
=3D3D
Is
=3D3D3D
>>>  =3D3D20
>>>
>>
>>this
>>
>>=3D3D20
>>
>>
>>>incorrect?
>>>
>>>
>>>{{{{{No.  Phase jitter is always accumulated regardless open-loop
>=3D3D20
> or=3D3D3D20
>=3D3D20
>>>closed-loop.  Closing the loop does attenuate the phase error
>=3D3D20
> within=3D3D3D20
>=3D3D20
>>>the bandwidth, but RMS RJ does not go to zero.  }}}}}
>>>
>>>  =3D3D20
>>>
>>
>>We agree that feedback cannot drive jitter to zero.  I remain at
>=3D3D20
> odds=3D3D3D20
>=3D3D20
>>with your blanket assertion that phase jitter accumulates in a
>=3D3D20
> closed=3D3D3D20
>=3D3D20
>>loop as well as an open loop.  Jitter is a noise term, and all =3D
my=3D3D3D20
>>references state that a feedback loop works to reduce noise terms
of=3D3D3D20
>>the elements within the loop.  Do you have a reference as to why
>=3D3D20
> this=3D3D3D20
>=3D3D20
>>would not be so in this situation?
>>
>>It appears we agree that the loop acts to reduce phase error which
>=3D3D20
> is=3D3D3D20
>=3D3D20
>>what we care about and where Chris' complaint came from.  We =3D3D
appear=3D3D3D20
>>to also agree that as we slide down the GBW curve the amount =
of=3D3D3D20
>>correction shrinks.  Do we agree that well above the 0db crossing
>=3D3D20
> the=3D3D3D20
>=3D3D20
>>loop does almost nothing to adjust the VCO phase to match the=3D3D3D20
>>incoming data stream?  If we agree then I think Chris' point =
is=3D3D3D20
>>made.  If we don't, I would like to know why.  It may be for =3D
the=3D3D3D20
>>particular standards that Chris is unhappy about that other
concerns=3D3D3D20
>>drove the cut-off frequencies selected.  But from the narrow=3D3D3D20
>>perspective of the PLL bandwidth impact on CDR function I see his
>=3D3D20
> point.
>=3D3D20
>>=3D3D20
>>
>>
>>>If so, why?  Absent feedback, I=3D3D3D3D20
>>>expect the each inverter in the oscillator to exhibit 1/f noise =
=3D3D3D
>>>  =3D3D20
>>>
>>
>>like=3D3D3D3D20
>>
>>=3D3D20
>>
>>
>>>any other amplifier no matter how clean the power supply is.  Do =3D
=3D3D3D
>>>  =3D3D20
>>>
>>
>>you=3D3D3D3D20
>>
>>=3D3D20
>>
>>
>>>agree?  If not, why?
>>>
>>>{{{{{Sure.  But with feedback, the same is still true that the
>=3D3D20
> random=3D3D3D20
>=3D3D20
>>>noise is still present.  That is not the point of the argument.
}}}}}
>>>
>>>  =3D3D20
>>>
>>
>>I am not sure if we agree that feedback attenuates all types of noise.
>>Do we?
>>
>>
>>=3D3D20
>>
>>
>>>I agree that designing a stable VCO and feeding it with clean
>=3D3D20
> low=3D3D3D3D20=3D3D3D20
>=3D3D20
>>>impedance power are important towards achieving low jitter.  But =
=3D3D
I=3D3D3D20
>>>am=3D3D3D3D20 having difficulty following the apparent idea that
>=3D3D20
> achieving=3D3D3D20
>=3D3D20
>>>those=3D3D3D3D20 goals eliminates jitter components as opposed to =
=3D3D
reducing
=3D3D3D
>>>  =3D3D20
>>>
>>
>>them
>>
>>=3D3D20
>>
>>
>>>to=3D3D3D3D20 small values.  Is there a conflict between semantics of
>=3D3D20
> "very=3D3D3D20
>=3D3D20
>>>small"=3D3D3D3D20 and "zero"?
>>>
>>>
>>>{{{{{I never said that jitter can be eliminated.  I only said that
>=3D3D20
> RMS=3D3D3D20
>=3D3D20
>>>jitter is bounded for both VCO and PLL.  Alfred made the assertion
>=3D3D20
> that
>=3D3D20
>>>  =3D3D20
>>>
>>
>>=3D3D20
>>
>>
>>>VCO has unbounded rms jitter, but PLL has bounded rms jitter.  =3D3D
The=3D3D3D20
>>>funny equations you guys put out do not help with your arguments
at=3D3D3D20
>>>all. }}}}}
>>>
>>>  =3D3D20
>>>
>>
>>Al is very capable and knowledgeable in this area.  I do not =3D3D
speak=3D3D3D20
>>for him.  It would be a lot easier to reach a common understanding
>=3D3D20
> if=3D3D3D20
>=3D3D20
>>you could tone down the open hostility.
>>
>>
>>=3D3D20
>>
>>
>>>Regards,
>>>
>>>
>>>Steve.
>>>  =3D3D20
>>>
>>
>>snip=3D3D3D20
>>
>>=3D3D20
>>
>=3D3D20
>=3D3D20

--=3D3D20
Istvan Novak            Sun Microsystems, Inc.
Istvan.Novak@xxxxxxx    Workgroup Servers, BDT Group,
One Network Drive, Burlington, MA 01803
Phone: (781) 442 0340
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```