[SI-LIST] Re: Jitter Variation for Fast & Slow ASIC's
- From: Joseph.Schachner@xxxxxxxxxxxxxxxxxx
- To: ah.vinod@xxxxxxxxx
- Date: Thu, 29 Aug 2013 10:14:14 -0400
Re: "But unable to understand, how can fast switching transistor result in
less jitter as compared to slow switching transistor."
There are probably better answers than this, but here's one way slower
switching can result in higher jitter: If the voltage noise on the signal
is greater than nothing, and that must be true, then slower transitions
turn that voltage noise into larger time domain jitter.
I don't know what you're looking at so here is a totally contrived
example. Suppose there is just 3mV rms noise. That means in a short span
of time there could be 10mV excursions. 3 sigma is not rare.
Now, suppose we have transitions rising from 0 to 3V, one in 100ps, the
other in 200ps. The slope of the first is 3V/100ps = 30e9V/s or 30V/ns.
The slope of the second is 3V/200ps which of course is 15e9V/s or 15V/ns.
So, suppose that as the transition is rising toward the threshold,
sometimes a 10mV positive noise excursion makes it cross the threshold
early. How much time shift could that cause?
For the 100ps transition: 10mV / 30e9V/s = 0.333ps
For the 200ps transition: 10mV / 15e9V/s = 0.667ps
And similarly it could also happen that as the transition approaches the
threshold a negative going noise excursion delays the time when the
threshold is actually crossed.
Summary: Voltage noise translates into timing jitter. The amount of
jitter it causes is more for slower transitions (it is inversely
proportional to the slope of the transition).
--- Joe S.
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