[SI-LIST] Re: Is Impedance Enough for Describing the PDS?
- From: Ray Anderson <reanderson@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 16 Jul 2004 13:40:04 -0700
Chris-
I think you are in violent agreement with Larry and others with regard
to this thread's topic.
You are saying that p/s dynamic response is just as important as the
impedance. If you look at the output impedance of a VRM it will exhibit
some low impedance from DC up to some corner frequency that is a
function of the loop dynamics (i.e. loop bandwidth) . Above that corner
frequency the impedance will begin to climb. VRM's that have a higher
clock frequency usually have a correspondingly higher corner frequency
at which the impedance starts to increase. Hence, one can argue that
VRM's with higher clock frequencies maintain a low output impedance to
higher frequencies than VRMs with lower clock frequencies.
It follows as you have pointed out, that a smaller amount of bulk
capacitance is required to maintain a low impedance over the low end of
the spectrum when the VRM maintains it's impedance at a low value to a
higher frequency.
As far as "one of these days" a VRM with a 10-100MHz clock rate becoming
available, I think "one of these days" has already arrived. (Check out
some of the available VRM's aimed at the military market and the
multi-phase switchers that have a high "effective" clock rate due to the
multi-phase architecture).
So, are we in violent agreement or am I misinterpreting your statement?
-Ray
Chris Cheng wrote:
>I think the power supply response is just as important as the impedance. If
>you can get your DC/DC to beat faster, the amount of bulk caps needed to
>hold the low end of the impedance can be minimized. One of these days, some
>very smart people will come out with a 10-100MHz DC/DC. Things will get very
>interesting.
>
>
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