[SI-LIST] Re: Invite: Challenges, Opportunities and Solutions for Multi-Gigabit SerDes Seminar
- From: steve weir <weirsi@xxxxxxxxxx>
- To: arpad.muranyi@xxxxxxxxx, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 26 Apr 2005 11:31:02 -0700
Arpad, but it means a trip to London or Munich! Don't we all need
vacations, er education???
Don't worry, the stupid user login will probably inhibit 50% of the people
who might otherwise register.
Regards,
Steve
At 11:10 AM 4/26/2005 -0700, Muranyi, Arpad wrote:
>I know this may be a sensitive subject and one can argue it both ways,
>but I think this recent posting is going a little overboard. I agree
>that the seminars advertised here are useful to the SI community, but
>I object against the "Register now" link towards the bottom which is
>clearly a self serving advertisement which is a NO-NO on this forum.
>
>Aside from cleaning out the abundant junk (spacer.gif, etc...) the
>poster should have kept it to a minimum information with perhaps just
>one link and no more...
>
>Arpad
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>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
>On Behalf Of Ken Reid
>Sent: Monday, April 25, 2005 9:39 AM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Invite: Challenges, Opportunities and Solutions for =
>Multi-Gigabit SerDes Seminar
>
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>"Challenges, Opportunities, and Solutions for Multi-Gigabit SerDes"
>Design Seminar - presented by Cadence, Rambus, Denali and Catalyst=20
>
>Tuesday, May 10 2005 at 1:00pm in Bracknell
><http://www.cadence-europe.com/design_seminar> =20
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>Thursday, May 12 2005 at 1:00pm in Munich
><http://www.cadence-europe.com/design_seminar> =20
>
>In this Seminar specialists from Cadence, Rambus, Denali and Catalyst
>will discuss chip, board, and system design & test considerations for
>integrated solutions for high speed communication applications. We have
>brought together enabling technologies from each company to develop a
>Vertical approach for high speed communication. We will discuss the
>Vertical Solution for PCI Express and provide demonstrations from each
>company showing how this can help increase your productivity.=20
>
>This will be of interest to anyone involved with the design or test of
>Gigabit Ethernet, XAUI, Backplane, PCI Express(tm), Serial RapidIO(tm),
>and other serial link based chips and systems, specifically: I/O
>Designers, Chip Architects, System Designers, Technical Managers, Test &
>Validation Engineers.=20
>
>This seminar will be followed by a Drinks Reception when Technical
>experts from each company will be available to provide demonstrations
>and answer questions.=20
>
>Register now <http://www.cadence-europe.com/design_seminar> for this
>valuable seminar.
>
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>(c) 2005 Cadence Design Systems <http://www.cadence.com/trademarks.aspx>
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>Privacy <http://www.cadence-europe.com/privacy.cfm>=20
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