[SI-LIST] Invite: Challenges, Opportunities and Solutions for Multi-Gigabit SerDes Seminar
- From: "Ken Reid" <kreid@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 25 Apr 2005 17:38:50 +0100
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"Challenges, Opportunities, and Solutions for Multi-Gigabit SerDes"
Design Seminar - presented by Cadence, Rambus, Denali and Catalyst
Tuesday, May 10 2005 at 1:00pm in Bracknell
<http://www.cadence-europe.com/design_seminar>
Thursday, May 12 2005 at 1:00pm in Munich
<http://www.cadence-europe.com/design_seminar>
In this Seminar specialists from Cadence, Rambus, Denali and Catalyst
will discuss chip, board, and system design & test considerations for
integrated solutions for high speed communication applications. We have
brought together enabling technologies from each company to develop a
Vertical approach for high speed communication. We will discuss the
Vertical Solution for PCI Express and provide demonstrations from each
company showing how this can help increase your productivity.
This will be of interest to anyone involved with the design or test of
Gigabit Ethernet, XAUI, Backplane, PCI Express(tm), Serial RapidIO(tm),
and other serial link based chips and systems, specifically: I/O
Designers, Chip Architects, System Designers, Technical Managers, Test &
Validation Engineers.
This seminar will be followed by a Drinks Reception when Technical
experts from each company will be available to provide demonstrations
and answer questions.
Register now <http://www.cadence-europe.com/design_seminar> for this
valuable seminar.
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(c) 2005 Cadence Design Systems <http://www.cadence.com/trademarks.aspx>
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