[SI-LIST] Re: Interpretation of XTK results
- From: "Bill Hargin" <billh@xxxxxxxxxxxxxxxxxxxxxxx>
- To: <joeyoung10@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 26 Mar 2002 13:56:19 -0800
Hi Joe:
----------------------------------------------------------
Delay Rise(ns) Delay Fall(ns) Overshoot(V) Osc(V) ERROR
min max min max Low High MAX
============================================================================
=
SDRAM Input 31.11 31.91 31.21 31.97 -0.00 -0.00 0.00 D
-----------------------------------------------------------------------
XTK is reporting a (D)elay error on your SDRAM_clk net, but it appears that
you may not have everything set up properly.
"Buff Outp VM (lh) 0.00 VM (hl) 0.00"
XTK should be getting "VM" (from XTK's .MOD IC model) from Vmeas in an
associated IBIS model, if available. It looks like the model creator,
however, didn't include "VM" in the driver model. To make the associated
delay calculations, XTK would need to subtract the time that the Input
voltage crosses Vinl and Vinh to determine min and max delays. If data is
lacking for the driver, I would look to verify that Vinl and Vinh values are
included in the input model, as well. If the data are there (for the
input), you can take their average, plugging this in for Vmeas, lacking
better data from the IC vendor.
If Vmeas (VM), Vinl, and Vinh were all OK (they don't appear to be), XTK is
telling you that -- on the rising edge -- the Input voltage crossed Vil (Min
Delay) at 31.11 ns from the time the Output voltage crossed Vmeas (the
earliest that the receiver could see a "1"). Similarly, the Input voltage
crossed Vih (Max Delay) at 31.91 ns from the time the Output voltage crossed
Vmeas (the latest we would expect the receiver to see a "1").
Similar reasoning would follow for the falling edge.
These results are compared to thresholds that you provide XTK with, and --
if you fall outside the thresholds -- you end up with flags in the ERROR
column.
If you have no idea what Vinl and Vinh are, you can use .75 x the rail
voltage for Vinh, and .25 x the rail voltage for Vinl, and .50 x for Vmeas,
but these would just be qualitative guesses. The manufacturer should
provide this data.
Best Regards,
Bill Hargin
Direct: 425-702-0744
Fax: 425-702-0305
Cognition Consulting
Electronic Design Software and Consulting
http://www.CognitionConsulting.com
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Joe Young
> Sent: Tuesday, March 26, 2002 1:13 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Interpretation of XTK results
>
>
>
> Hi experts,
> I am a new guy for XTK. I don't know whether i am
> interpreting the XTK results properly. I have copied results in
> this email. Could anybody please explain me the results?
> ----------------------------------------------------------
> Delay Rise(ns) Delay Fall(ns) Overshoot(V)
> Osc(V) ERROR
> min max min max Low High MAX
> ==================================================================
> ===========
> SDRAM_clk
> Buff Outp VM (lh) 0.00 VM (hl) 0.00 Vgb 0.00 0.00
> Vcb 0.00 0.00
> SDRAM Input 31.11 31.91 31.21 31.97 -0.00 -0.00
> 0.00 D
> SDRAM_clk 31.11 31.91 31.21 31.97 -0.00 -0.00
> 0.00 D
> -----------------------------------------------------------------------
> ----------------------------------------------------------------------
>
> rgds,
> Joe
>
>
> 2,000,000,000 Web Pages--you only need 1. Save time with My Lycos.
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