[SI-LIST] Re: Inter-plane capacitance
- From: "Kai Keskinen" <kalevi@xxxxxxxxxx>
- To: <makanu2000@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 14 Jun 2006 18:16:45 -0400
If you are failing high pot, you do not have an issue with inter-plane
capacitance. You have some medium resistive path between your hazardous
voltage line and the board digital ground. It is either a fault in the
board shop due to poor etching caused by a multitude of possible reasons, a
conductive impurity on the board surface (something like washable solder
flux that was not washed away properly) or some layout issue related to
spacing, probably on the surface layers. When high potting, turn off the
lights and you may actually see where the breakdown occurs.
You can calculate your interplane capacitance if you open up your first year
EM text book and look up parallel plate capacitance.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Anupama
Sent: Wednesday, June 14, 2006 7:30 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Inter-plane capacitance
Hi
Is there any tool available to measure the inter-plane capacitance
specially for internal VCC and GND plane. in our case We are observing
high leakage current while hi-pot testing ..... can we measure with
Hyperlynx or any specific formula....
Thanks in advance.
Mak
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