Hello, Ray: Thank you for sharing your thoughts. Purely relying on 3D/2.5D field solver does not sounds practical for a complicated BGA. The challenge is short of full packaging characterization, it's difficult to predict the worst case scenario in terms of simultaneous switching output (driving) and input (receiving) noise and how these noise may "crosstalk" into other sensitive parts of the circuits such as analogue power supply for serdes transceiver. Regards Perry ======================================= Perry Qu Design & Qualification, Alcatel-Lucent Canada Inc. 600 March Road, Ottawa ON, K2K 2E6, Canada DID: 613-7846720 Fax: 613-5993642 Email: perry.qu@xxxxxxxxxxxxxxxxxx ======================================= ________________________________ From: Ray Anderson [mailto:ray.anderson@xxxxxxxxxx] Sent: Tuesday, January 16, 2007 2:57 PM To: si-list Cc: QU Perry; Mark Alexander; Ray Anderson Subject: RE: [SI-LIST] Re: Internal package aggressors/PCB routing Perry- You bring up a very important and timely issue. As you point out it isn't a trivial matter to accurately model the effects of the return current loop inside a dense BGA package. A typical RLC extraction performed by a quasi-static tool may not produce a model that is adequate for accurately investigating the effects of the loop in a full package. While these RLC models are quite good for some purposes (time of flight, reflections, simple crosstalk), their use in evaluating the effects of return current paths is quite often dubious. A full-wave 3D extraction tool such as HFSS or Owave or other similar FEM tools will produce the most accurate data that includes the effects of return path imperfections in the generated s-parameters, however it is currently impractical to perform a full package extraction with this class of tool due to the vast size of memory required and the run time involved. The typical 3D full-wave extractor doesn't handle power planes very efficiently. For less than 'full package' extractions with a reasonable # of nets you can analyze the planar structure separately with a tool optimized for plane extraction and then combine the s-parameters thus generated with the parameters from the signal net extraction. However, as mentioned, this still isn't going to get you to a full package with several thousand nets. A 'second best' option is to utilize a tool like PowerSI. This can handle both the planes and signal nets in an efficient manner, and in theory could extract a full package model given enough RAM in a 'useful' amount of time (i.e. a couple weeks vs a couple months). This approach has limited accuracy above about 6 GHz. However as a practical matter we find the extraction of a full bank model (in the case of our FPGAs that is either 40 or 64 drivers) to be about the largest model that is practical. Even if you could generate a full package model in a reasonable amount of time that accurately models all the return current effects it would be huge. Assume your chip has only 500 signal nets. That would be 1000 ports. Now add the ports for the PDNs, that could easily be another 50 ports. Now take your 1050 port Touchstone s-parameter model and attempt to do a useful transient simulation in Hspice or Nspice or ADS or whatever your favorite simulator is. Good luck!...... This is a huge topic and is something we are currently investigating. -Ray Anderson Raymond Anderson Senior Signal Integrity Staff Engineer Advanced Platforms Group Advanced Products Division Product Technology Department Package Design Engineering Xilinx Inc. 2100 Logic Drive San Jose, California 95124 (408) 626-6277 -----Original Message----- From: QU Perry [mailto:Perry.Qu@xxxxxxxxxxxxxxxxxx] Sent: Tuesday, January 16, 2007 6:48 AM To: Chris.Cheng@xxxxxxxxxxxx; si-list; Ray Anderson; Mark Alexander Subject: RE: [SI-LIST] Re: Internal package aggressors/PCB routing Chris: You hit this on the nail. I once had a look of a mcm packaging design from a IC vendor and I saw exactly what you mentioned: jump of return path all over the place and what strike me the most is at the area close to flip chip bumps, where large copper clearance cut off the return path and you get about one ground bridge for every 20 or so bumps, so all the return current for those 20 signals has to crowd through that bridge including giga bit signals. How to model and predict the effects of large return loop on a full packaging scale as Ray mentioned is something I'm curious. For me it seems to very difficult to predict where the return current flows for a complicated BGA packaging. A full wave field solver should help but I'm not sure whether it can handle the complexity. Probably Ray and Mark can elaborate a bit more in details ? Thanks Perry ======================================= Perry Qu Design & Qualification, Alcatel-Lucent Canada Inc. 600 March Road, Ottawa ON, K2K 2E6, Canada DID: 613-7846720 Fax: 613-5993642 Email: perry.qu@xxxxxxxxxxxxxxxxxx ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu