[SI-LIST] Re: Interfacing DDR 400 DRAM Chips to Xilinx Virtex II FPGA.
- From: steve weir <weirsp@xxxxxxxxxx>
- To: sivakumar_skm@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Mon, 15 Sep 2003 07:48:56 -0700
Siva,
It is a little bit of an undertaking, but has been done successfully. It
can be done using -6 speed grade parts, careful floor planning, local clock
routing, and some realistic limitations on how fancy a controller function
you want. For example, score boarding open banks to dynamically determine
when to precharge requires too many levels of combinatorial logic to run at
200MHz.
You need an FPGA guru, and/or a lot of hand holding from Xilinx. If you
have already laid your board out, you may have to accept either reduced
performance or a board spin.
Regards,
Steve.
At 07:30 AM 9/15/2003 -0700, Siva kumar wrote:
>Hi Gurus,
> I need to interface DDR400 DRAM chips and
>DDR333 SO-DIMM Module to a Virtex II FPGA.Can anybody
>successfully implemented this speed using Virtex II
>FPGA?.
>
>Any inputs timing calculations?.
>
>Thanks and Regards,
>siva
>
>
>
>
>
>
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