[SI-LIST] Re: Inserion loss of fr4 , 50 ohm trace .

From: Hassan O. Ali <hassan@xxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>, steve weir <weirsi@xxxxxxxxxx>
Date: Sun, 24 Nov 2013 11:09:33 -0500
will be more fringing fields in air than in microstrip case. If the
gap was narrow, certainly more field will be in the lossy dielectric
and that wouldn't help with the loss.
 Best regards,
 Hassan.
 On Sun 11/24/13  9:22 AM , steve weir weirsi@xxxxxxxxxx sent:
 Hassan are you trying to say that lossy material can help suppress  
 resonant dips, in which case I agree, or are you trying to say
something  
 else? 
 Steve. 
 On 11/24/2013 7:07 AM, Hassan O. Ali wrote: 
 > lossy FR-4 can also help in decreasing the overall loss. It still 
 > remains to be confirmed which of the two loss mechanisms is worse.
 >   BTW, this is the second time I post on the SI-List and I see my 
 > message truncated at the top. Can the list administrator look into

 > this? I use a webmail tool to send the messages. I've
intentionally 
 > added a bunch of  ">" above to see if it can help. For reference, 
 > I've attached below my complete message. 
 >   Best regards, 
 >   Hassan. 
 >   ------- 
 >   Sunil, 
 >   You've received excellent contributions from list members
regarding 
 > your  line loss issue. You're experiencing around 2.2dB/inch loss 
 > discrepancy  between measurement and simulation. That huge 
 > discrepancy seems to be  caused by several factors. No single
factor 
 > can explain such a huge  discrepancy. 
 >   From the Shlepnev/McMorrow paper (and various cited references),

 > ENIG  plating should contribute less than 1dB/inch of additional
loss 
 > even in  the worst case at the problem frequencies. You may also
need 
 > to  double-check your insertion loss curve if you're seeing
similar 
 > resonant  behavior at around 2.7GHz. If you do, certainly ENIG
could 
 > be an issue. 
 >   Incorrect dissipation factor (dielectric loss tangent) of FR-4 
 > suggested  by Istvan is another very probable cause. 0.035 sounds
to 
 > be a good  number to use and easily may double your loss. There
are 
 > also  substantial material property variations depending on the 
 > supplier. 
 >   Scott pointed out another important consideration - excitation
and 
 > the  measurement mode. Coplanar waveguide mode may not be the mode

 > that  you're simulating with. Confirm the mode in HFSS through
Port 
 > Field  Display. Also make sure that you've chosen "Solve Inside"
at 
 > least for  the line trace and coplanar grounds. 
 >   I assume your HFSS model includes a mated coaxial connector. If
not, 
 >   that's another source of additional unaccounted loss. And
depending 
 > on  the type of coaxial connector you're using and the way it was 
 > installed  on the test board, you can have other secondary
effects. 
 > For example,  observe if there is an air gap between the connector

 > body and the PCB  pad it's soldered to. Or check if the connector 
 > ground is well connected  to the PCB ground. Even an air gap of
less 
 > than 1 mil can have  significant insertion loss effects especially
at 
 > higher frequencies. 
 >   Metal surface roughness is also a secondary effect for the 
 > frequencies  of your interest. For normal PCB fab processes I
don't 
 > think there is  much surface roughness induced loss at such low 
 > frequencies of your  interest. 
 >   As a general comment, for FR-4, it's not always true that a
wider 
 > trace  could give you a lower loss. You may need to re-consider
your 
 > choice of  dielectric thickness and trace width to achieve a lower

 > loss solution  for your line impedance target. 
 >   Best regards, 
 >   Hassan. 
 >   On Sun 11/24/13  7:39 AM , Scott McMorrow scott@xxxxxxxxxxxxx
[1] sent: 
 >   Ali 
 >   All the measurement and simulation data that I've seen for ENIG
is 
 > based on microstrip lines.  In the Case of CPW, I expect losses
will 
 > be even higher, depending on the substrate thickness.  A CPW
design 
 > with a thick substrate will increase the percentage of signal
energy 
 > carried in the co-planar air gaps.  Since this is covered with 
 > Nickel, it will necessarily increase the amount of loss 
 > proportionally over microstrip. 
 >   Of course, thick substrates also make for difficult
measurements, 
 > and the launching of additional modes. 
 >   On Sun, Nov 24, 2013 at 1:45 AM, Hassan O. Ali  wrote: 
 >   discrepancy between measurement and simulation. That huge 
 > discrepancy 
 >   seems to be caused by several factors. No single factor can
explain 
 >   such a huge discrepancy. 
 >    From the Shlepnev/McMorrow paper (and various cited
references), 
 >   ENIG plating should contribute less than 1dB/inch of additional
loss 
 >   even in the worst case at the problem frequencies. You may also
need 
 >   to double-check your insertion loss curve if you're seeing
similar 
 >   resonant behavior at around 2.7GHz. If you do, certainly ENIG
could 
 >   be an issue. 
 >    Incorrect dissipation factor (dielectric loss tangent) of FR-4 
 >   suggested by Istvan is another very probable cause. 0.035 sounds
to 
 >   be a good number to use and easily may double your loss. There
are 
 >   also substantial material property variations depending on the 
 >   supplier. 
 >    Scott pointed out another important consideration - excitation
and 
 >   the measurement mode. Coplanar waveguide mode may not be the
mode 
 >   that you're simulating with. Confirm the mode in HFSS through
Port 
 >   Field Display. Also make sure that you've chosen "Solve Inside"
at 
 >   least for the line trace and coplanar grounds. 
 >    I assume your HFSS model includes a mated coaxial connector. If

 > not, 
 >   that's another source of additional unaccounted loss. And
depending 
 > on 
 >   the type of coaxial connector you're using and the way it was 
 >   installed on the test board, you can have other secondary
effects. 
 >   For example, observe if there is an air gap between the
connector 
 >   body and the PCB pad it's soldered to. Or check if the connector

 >   ground is well connected to the PCB ground. Even an air gap of
less 
 >   than 1 mil can have significant insertion loss effects
especially at 
 >   higher frequencies. 
 >    Metal surface roughness is also a secondary effect for the 
 >   frequencies of your interest. For normal PCB fab processes I
don't 
 >   think there is much surface roughness induced loss at such low 
 >   frequencies of your interest. 
 >    As a general comment, for FR-4, it's not always true that a
wider 
 >   trace could give you a lower loss. You may need to re-consider
your 
 >   choice of dielectric thickness and trace width to achieve a
lower 
 >   loss solution for your line impedance target. 
 >    Best regards, 
 >    Hassan. 
 >    On Sat 11/23/13 10:50 AM , Scott McMorrow scott@xxxxxxxxxxxxx
[2] [2] 
 > sent: 
 >    Steve 
 >    there is only one simulator that I know of that can simulate
ENIG 
 >    correctly. It is Simberian Simbeor, where Yuriy Shlepnev
introduced 
 >   the 
 >    necessary Landau-Lifshits Ferromagnetic dispersion model based
on 
 >   our 
 >    research. 
 >    Nickel models that I have seen in other simulators uses only 
 >   magnetic 
 >    permeability, which will miss the dispersive resonance between
2 
 > and 
 >   3.5 
 >    GHz, centered around 2.7 GHz. 
 >    Scott 
 >    Scott 
 >    On Sat, Nov 23, 2013 at 11:26 AM, steve weir  wrote: 
 >    > The demon nickel impact should have shown up in your
simulation. 
 >   Didn't 
 >    > you include the Ni and Au of the ENIG surface finish in your 
 >   model? 
 >    > 
 >    > Steve. 
 >    > On 11/23/2013 8:05 AM, sunil bharadwaz wrote: 
 >    > > Thanks Scott !! Yes , ENIG was used . I'am not suspecting
the 
 >   CPW , as 
 >    > the 50 ohms 
 >    > > is showing correctly when tested with VNA . 
 >    > > Regards 
 >    > > Sunil. 
 >    > > 
 >    > > 
 >    > > 
 >    > > 
 >    > > 
 >    > > On , sunil bharadwaz  wrote: 
 >    > > 
 >    > > Thanks Bala !! I will try that . Yes , the cable losses
were 
 >   already 
 >    > factored in & there are no Via's 
 >    > > on the RF line . 
 >    > > 
 >    > > Regards 
 >    > > Sunil 
 >    > > 
 >    > > 
 >    > > 
 >    > > 
 >    > > 
 >    > > On Saturday, November 23, 2013 7:15 PM, bala 
 >    > wrote: 
 >    > > 
 >    > > Sunil, 
 >    > > I would recommend to consider copper roughness and double
check 
 >   your via 
 >    > and coplanar modeling in your simulation.I believe you
considered 
 >   the loss 
 >    > of your measurement cable.or simply generate s-parameter
model 
 >   from VNA, 
 >    >  check symmetric and passivity ,put that model in your sim
setup 
 >   and see 
 >    > whats the loss.You shall definitely  get an idea. 
 >    > > Regards 
 >    > > bala 
 >    > > On 23 Nov 2013 18:33, "sunil bharadwaz" 
 >    > wrote: 
 >    > > 
 >    > > Hi friends , 
 >    > >> We are designing a dual band receiver ( 2.4 Ghz & 5.5 Ghz
) on 
 >   a Fr4 
 >    > substrate . 
 >    > >> 
 >    > >> The length of the 50 ohm RF trace ( CPW - 15 mil trace
width & 
 >   18 mil 
 >    > spacing to ground ) , 
 >    > >> is approximately 5 cms .We have simulated this 5 cms long
CPW 
 >   trace on 
 >    > HFSS using DK of 
 >    > >> 
 >    > >> 4.4 & DF  of 0.018 . The loss reported was about 1.6 dB . 
 >    > >> 
 >    > >> We have received the actual board , which shows about 6 dB

 > loss 
 >   for the 
 >    > same trace (actual measurement on VNA) 
 >    > >> 
 >    > >> Measured the 50 ohm trace with TDR . It shows about 53 to
54 
 >   ohms . The 
 >    > fab report is also 
 >    > >> in sync with the measurement on the impedance front .The
test 
 >   coupon ( 
 >    > from fab  )also shows 
 >    > >> the right impedance . 
 >    > >> 
 >    > >> Why are we seeing such a huge insertion loss ? The DF of
0.018 
 >   seems to 
 >    > be correct . 
 >    > >> I have double checked this number , with the fab . 
 >    > >> 
 >    > >> Can some one ( pls ) explain the inconsistency between the

 >   simulated & 
 >    > actual results  ? 
 >    > >> 
 >    > >> Best Regards 
 >    > >> Sunil.Bh 
 >    > >> 
 >  
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