Hello,
For digital signals, which are wide band (as opposed to centered on a specific
frequency), i.e. consist of a wide range mixture of frequencies/wavelengths,
there is no such thing as "lambda/4", so that way of matching is not applicable
here.
200ps on microstrip corresponds to a distance of roughly 4cm. The center pin of
an SMA connector (and thus the length of the mismatched line section) is about
10x shorter.
The fact that the section is short relative to the rise time means you can to a
good degree of accuracy consider the mismatch as a lumped parasitic. I would
run a few simulations with a simple transmission line calculator to find the
approximate impedance and propagation delay of this section based on the
manufacturer recommended footprint (because the connector is wider than your
trace you will have too much capacitance, i.e. a capacitive parasitic). With
these numbers you can then do a simple simulation in e.g. PSpice or LT Spice to
get a feel for the size of the reflections and loss caused by this section.
Rough rule of thumb, reflection in percent is approximately Tc/Tr, with Tc
being the time constant of the parasitic, Tr the rise time of the signal.
It may very well turn out reflection and loss are acceptable for your design -
in this case you are done but will sleep better.
Second, you could compensate a lumped capacitive parasitic with additional
inductance. One way would be to create a ground cutout below the center pin so
the next ground plane is further away and the impedance thus goes up. You'll
need at least a decent 2.5D simulator (e.g. Sonnect, but there are several
others) to create a decent model for this. Or you go the experimental route and
create a sample board with a few variations of this cutout.
In any case don't forget to stitch the shield of the SMA connector tightly to
the ground plane(s) with several vias.
Best regards,
Wolfgang
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Havermann, Gert
Sent: Tuesday, October 11, 2016 1:57 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Input Matching for SMA Connectors
Hi Hakim,
If you want the Transition from SMA to PCB as clean as possible, then you need
to run a 3D simulation and optimization of the Transition. You need to optimize
either the Stack-up, or the Footprint and void for a given Stack-up. For
tracewidth smaller than the Contact pad you need to add Cutouts/voids in the
Copper plane underneath the pad to compensate the capacitive impact of the pad.
Or you select a stack-up and a connector, and then ask the connector vendor to
provide a footprint for your Stack-up. A lot of Vendor do that for you free of
charge (Rosenberger, Southwest...) if the Projekt is interesting enough
(Volume).
Or you check the web for Design Studies about SMA to PCB Transition (there are
a lot of papers out there on this topic), and then Copy their Stack-up and
footprint (check if it is IP-free before designing it into a real Product).
Since it is only 5GHz, you might be able to just use the Vendors recommended
Footprint, but very often these aren't optimized at all. That’s the more
dangerous way.
Hope this helps
Gert
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Hakim Sellaoui
Sent: Tuesday, October 11, 2016 1:25 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Input Matching for SMA Connectors
Hi all,
I'm designing a test board that will have differential trace widths of 4 mil
and I want to connect SMA connectors to them, but I'm not sure what connector
would be suitable as the ones I've found have connector widths that are neither
equal to or smaller than the trace widths, as well as the recommended pad sizes
are much larger. For an RF design I did at Uni, I just added a quarter wave
transformer to provide the matching at the operating frequency; is it still
possible to do this with a high-speed design with a 200 ps rise time (5 GHz)
signal?
Or can anyone recommended a way to connect VNA coaxial cables to a PCB with
trace widths around 4 mils, such that the Zo is maintained.
Thanks,
--
Hakim Sellaoui
Associate Hardware Engineer
DisplayLink (UK) Limited
Tel: +44 (0)1223 443920
Fax: +44 (0)1223 443921
E: hakim.sellaoui@xxxxxxxxxxxxxxx<mailto:hakim.sellaoui@xxxxxxxxxxxxxxx>
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