[SI-LIST] Re: Input Clock phase noise and TX eye closurein SERDES

  • From: john <johndp@xxxxxxxx>
  • To: al@xxxxxxxxxxxxx
  • Date: Mon, 07 Feb 2005 22:30:46 +0000

Alfred, Craig

thanks for the input, my problem is I do not yet have any silicon to 
measure and it's likely to be
a year to 18 months away, this is very much at the definition stage. 
What I'm trying
to do is get to a clock phase noise figure, for just the TX PLL 
reference clock so that I can
compare those requirements to other parts of the system (very high speed 
ADCs for one).
Obviously the design will be refined and as parts of the system come 
together I can simulate
and measure as appropriate to get a better feel of the link dynamics.

The lower limit of the specification puzzles me , if I integrate over the
ranges suggested by Craig, the higher the lower cutoff frequency, the  less
noise power, obviously because the area under the phase noise curve is 
increasingly
small.

Regards

John


Alfred P. Neves wrote:

>John,
>
>An alternative method (and much easier I think) of using integration
>transmitter PLL phase noise to arrive at accumulated, N-clock, or Phase
>Jitter is to use autocorrelation analysis using a TIA approach
>measureing multiple UI's of jitter.  Reasoning is that loop dynamics
>change based on the data pattern such that every pattern yields a
>different PLL transfer function.  Another consideration is the jitter
>due to charge pump leakage and Duty Cycle distortion, where the DCD
>doesn't fit into the phase noise analysis easily but is very much part
>of the jitter picture.  
>
>I always use a host of patterns when testing transmitter loop dynamics,
>including 2T through 5T clocks, K28.5, CJTPATS and general idle
>patterns.  Every data sequence yields a different loop dynamic for
>charge pump type PLL's since the update rate and transition density
>impact the loop dynamics.   
>
>By measuring the N-clock jitter the variance record and autocorrelation
>sequence can be established such that the autocorrelation is the inverse
>FFT of the PLL loop response.  Then the integration is simple over any
>specified bandwidth, and you additionally can directly examine
>cyclostationary periodic jitter due to charge pump leakage or substrate
>coupled energy.  Although I am not pushing anyones tools, I believe
>Wavecrest has some very good measure-based tools for PLL analysis.  
>
>References:
>
>Jitter in Ring Oscillators, John McNeill, IEEE, ISSC, June 1997
>Spectral Analysis of Time-Domain Phase Jitter Measurements, Moon,
>Mayaram, Stonick, ISCC, May 2002
>Also check out Mike Li's (and other authors) paper delivered at
>DesignCon last week on PCI Express.  This paper is probably available
>on the Wavecrest website.
>
>Also, note that Teraspeed is working on a sampling model of a transmit
>(and general clock) PLL loop where you can either measure or simulate
>the VCO open-loop response, PLL dynamics, and enter a transition
>density.  Given lowpass and high pass jitter masks you can arrive at
>either period or N-clock jitter.    Our correspondence to measurements
>using both a TIA and DSO has been very good.  
>
>
>
>
>Alfred P. Neves
>735 SE 16th Ave.
>Hillsboro, OR, 97123
>Office: (503) 679 2429
>Fax:    (503) 210 7727
>www.teraspeed.com
>al@xxxxxxxxxxxxx
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of johndp@xxxxxxxx
>Sent: Tuesday, February 01, 2005 7:57 AM
>To: Craig Twardy; johndp@xxxxxxxx
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Input Clock phase noise and TX eye closurein
>SERDES
>
>
>
>Craig,
>
>thanks for the reply.
>
>Say for the CDR in a FC-AL system, this has a low frequency 3dB point of
>Dbaud/1667 which for a 1.0625Gb/s link is 637KHz. If we combine this
>with the high pass function of the TX PLL we get a bandpass filter.
>Looking at the noise envelope of a good quality source, I can see that
>it remains relatively flat at about 145dBc/Hz above 1MHz, and so above
>the 3dB point of the TX PLL this is being attenuated at 20dB/decade. 
>
>The low frequency point still bothers me. With the break point at
>637Khz, the filtering effect is approx -36dB@10Khz, -56dB@1KHz,
>-76db@100Hz. The source phase noise is correspondingly -130dBc/Hz@10KHz,
>-100dBc/Hz@1KHz and  -65dBc/Hz @100Hz compared to -145dB/Hz @1MHz. So
>down to 1KHz the Filter roll off is faster than the rise in phase noise,
>but down at 100Hz, the phase noise is increasing faster than the roll
>off. So I still don't quite see how the lower limit is set.
>
>
>Regards
>
>John
>
>ctwardy@xxxxxxxxxx wrote:
>  
>
>>Hi John;
>>The lower limit will be defined by the bandwidth of the clock and data
>>    
>>
>
>  
>
>>recovery (CDR)of the receiver. The 10Khz (or 14-20Khz often) lower 
>>limit is used as most oscillators exhibit a large increase of phase 
>>noise below this frequency. Check out any phase noise plot of a stable
>>    
>>
>
>  
>
>>oscillator. Any CDR must deal with this.
>>Another way to look at it is to compare noise power over various
>>    
>>
>bandwidths.
>  
>
>>Compare the noise in
>>The integral from DC to F lowerlimit to the noise in the integral from
>>    
>>
>F
>  
>
>>lowerlimit to F upperlimit.
>>It most systems, I believe, that F upperlimit value is important in
>>determining the amount of random noise.
>>Craig
>>-----Original Message-----
>>From: si-list-bounce@xxxxxxxxxxxxx
>>    
>>
>[mailto:si-list-bounce@xxxxxxxxxxxxx] On
>  
>
>>Behalf Of johndp@xxxxxxxx
>>Sent: January 31, 2005 12:36 PM
>>To: si-list@xxxxxxxxxxxxx
>>Cc: johndp@xxxxxxxx
>>Subject: [SI-LIST] Input Clock phase noise and TX eye closurein SERDES
>>
>>I'm trying to relate reference clock phase noise to eye closure in a 
>>TX SERDES application. At this time I'm only interested in this area 
>>of the TX performance, as I'm trying to specify a clocking scheme for 
>>a much larger design. Assuming a second order TX PLL I can come up 
>>with an expression that relates the reference clock phase noise to the
>>    
>>
>
>  
>
>>transfer characteristic of the PLL. However I'm stuck with an 
>>intergral to work out the RMS jitter of the reference, the upper limit
>>    
>>
>
>  
>
>>of which is set by the 3dB point of the PLL, I'm not sure how to set 
>>the lower limit. I've read in a couple of places for example ref (1), 
>>a figure of 10KHz but can find no analytical basis for this figure.
>>
>>Any pointers much appreciated
>>
>>ref (1) Random Jitter - What Is Really Going On?
>>October 22, 2001 - CommsDesign.com
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