[SI-LIST] Info on Capacitive loading of devices
- From: "Sreejith Varma" <varma@xxxxxxxxxxxxxxx>
- To: "Signal Integrity" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 23 May 2002 17:21:42 +0530
HI All,
We have an ASIC working at 133MHz. Depending on the
requirement, this device can use 1 - 4 memory devices.
The device timings are specified for a load of 4 x Cio
(capacitance of IO pins) always.
Now the question is this.
If i put only one memory device (based on one application),
then can i put a capacitor 3 x Cio value in the path so
as to match the load and thus meet the timings?
If so what is the best place to put this capacitor? at the
source or at the end of trace?
If i am putting all four memory devices, what is the best
termination technology? The device has bidirectional pins.
Can i split the tracks into four and put 10 ohms and then
drive the four devices?
|-------/\/\/\----------------|\
| |/
|
|\____|-------/\/\/\----------------|\
|/ | |/
|
|-------/\/\/\----------------|\
| |/
|
|-------/\/\/\----------------|\
|/
FYI, The maximum trace length could be upto 6".
Greately appreciate any reply / pointers
Thanks in advance
sreejith
Paxonet communications
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
