[SI-LIST] Re: Importance of Package Height
- From: Larry Smith <ldsmith@xxxxxxxxxxxxxxxxxx>
- To: scott@xxxxxxxxxx, zhiping@xxxxxxxxx
- Date: Tue, 19 Mar 2002 13:46:43 -0800 (PST)
Zhiping and Scott - I cut off the bottom of this correspondence, it was
getting way to long.. I would like to think that I measured the
inductance ( L_cap+L_vias+L_plane) but probably a better phrase is that
I inferred what the inductance must have been from resonance
measurements.
The reason that most packaging systems resonate is because energy gets
alternately stored in electric and magnetic fields. At some frequency,
the energy sloshes back and forth between the two reactances. For a
measurement like this, there is always some equivalent capacitance and
some equivalent inductance. The capacitance is usually easy to
measure. The inductance is inferred from the capacitance and resonant
frequency.
It is sometimes difficult to identify exactly where the magnetic energy
is being stored. For most of our products, there are magnetic fields
stored in the cap, between the vias and between the power planes.
Magnetic energy is stored any place there is a current and you can
imagine the "right hand rule" directing B field lines of magnetic flux
around a conductor. Loop inductance is essentially the amount of B field
stored in the environment due to current going around some loop.
As Scott has very nicely pointed out below, a capacitor mounted in
close proximity to a return plane has less loop inductance than a cap
mounted on 50 Ohm (co-planer) transmission line. Even if the
conductive plane is floating (not part of a return path) eddy currents
will flow in the plane that cause opposing magnetic flux and reduce the
energy stored in the B field. Nature always tends towards the lowest
energy solution.
When we speak of loop inductance, it is best to visualize a loop of
current with a B field shooting through the loop. From a circuit and
simulation point of view, we reduce this loop inductance to a
bunch of partial self inductances with mutual inductance between all
the self inductances. We have to do this for accurate simulations but
this gets pretty complicated. (My friend Al Ruehli at IBM has made
a good career out of this!) It is easiest to just visualize current
going around a loop which stores up magnetic energy in a B field.
To directly answer Zhiping's question, my inductance measurement
discussed earlier is for total inductance, L_cap+L_vias+L_plane. My
caps are mounted very close to return planes.
For the cap mounted on 50 Ohm co-planer transmission line, the resonant
system and therefor total loop inductance involves L_cap plus some
undetermined inductance when magnetic energy is stored between the two
"50 Ohm" conductors as current escapes into the transmission line and
then returns as the system resonantes. That is the hard part. How far
did the current go? What was the loop area? Some nice FDTD analysis
could probably show us, but this loop is what determines the "ESL" of a
capacitor in the 50 Ohm environment.
In any case, the insertion of a return plane as close as possible to
the capacitor limits the size of the inductive loop and therefor loop
inductance. We have been able to take the capacitor off the mounting
fixture and measure the inductance of the mount itself. While this is
not a rigorously accurate measurement of the partial inductance of the
mount, we have been able to assign an inductance number to the mounting
structure and subtract that inductance from the mounted capacitor,
leaving just the "equivalent inductance" of the capacitor by itself.
I would not call this the ESL of the capacitor because now we are
dealing with a partial inductance and partial inductance doesn't have
much meaning outside the context of a loop. But it turns out that if
you use this partial inductance (for the capacitor) with the measured
or extracted partial inductance for the mounting structure, you get
really good model to hardware correlation. We have essentially cut the
loop in two pieces and assigned a partial inductance to each portion.
regards,
Larry Smith,
Sun Microsystems
> Date: Mon, 18 Mar 2002 16:42:46 -0800
> From: Zhiping Yang <zhiping@xxxxxxxxx>
> X-Accept-Language: en
> MIME-Version: 1.0
> To: scott@xxxxxxxxxx
> CC: Larry Smith <ldsmith@xxxxxxxxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Re: Importance of Package Height
> Content-Transfer-Encoding: 7bit
>
> Larry,
>
> In the measurement method you discribed below, you actually
> measured the total loop inductance ( L_cap+L_vias+L_plane),
> is it right? There should are some ways to seperate the L_vias
> and L_plane from the L_totlal, since L_cap is more meaningful
> for some PDS tools. It is always harder to define/extract partial
> inductance than loop inductance since loop indutance is always
> constant.
>
> Scott, I like your idea about the "effective inductance curve"
> related with the location of return current. Did you consider some
> special cases, such as on a mutil-layer board the plane just below
> the caps may not be the power/ground plane for this cap?
>
> Thanks.
>
> Zhiping
>
>
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> Date: Mon, 18 Mar 2002 14:33:26 -0800
> From: Scott McMorrow <scott@xxxxxxxxxx>
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> Subject: [SI-LIST] Re: Importance of Package Height
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>
> Larry,
>
> It seems to me that the inductance of a capacitor would be heavily
> influenced by the placement of a return plane below the capacitor. The
> mutual inductance between the capacitor and the plane would
> significantly lower the loop inductance. Is this possibly what is
> happening when capacitors are mounted on low impedance power planes?
> Here we have mutual inductance cancellation between the planes and
> mutual cancelation between the capacitor body and the closest plane.
>
> The problem we have is that for a capacitor the inductance is not
> defined until the loop is closed. The partial inductance of the
> capacitor body is heavily influenced by the method of measurement and
> the insertion into the plane. I am not sure that there is one method
> of measurement which can be used to extract the parameters for a
> capacitor, any more than there is one method which can be used to
> extract parameters for card edge connectors. In both cases, the loop
> inductance is dependant upon the the mutual inductance between the
> component and the underlying plane and the direction of return current
> flow through the plane. For the case of a measurement where a VNA is
> used with 50ohm launches into the capacitor, there is no return current
> on any plane and therefore, no mutual cancelation.
>
> For the case of a measurement in a loaded planar board, there is return
> current on the plane and and associated mutual cancelation which is
> beneficial to loop inductance.
>
> It might be possible to perform some theoretical modeling of a
> simplified capacitor structure with different measurement configurations
> using a 3D field solver to extract partial inductances and come up with
> some more general conclusions. My guess is that there will not be one
> inductance number that can be used for a specific capacitor, since it
> is such a poorly referenced structure in the first place. But, there
> is probably a range of inductances which are dependent upon the
> placement of planes in a board and whether or not currents flow between
> the capacitor and the plane.
>
> Since inductance is only defined around a loop, the only valid
> measurement is within the same structure where the device will be
> applied, so that all mutuals are correctly accounted for.
>
> regards,
>
> scott
>
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