[SI-LIST] Impedance deviation due to prepreg shrinking
- From: <caydin@xxxxxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 11 Jul 2005 12:28:10 EEST
Dear listl,
How prepreg layers effect the impedance of
a stripline? To clarify, my stack-up is;
S1
-------------- core
--------------
GND
-------------- prepreg
--------------
S2
-------------- core
--------------
VDD1
-------------- prepreg
--------------
S3
-------------- core
--------------
GND
-------------- prepreg
--------------
S4
-------------- core
--------------
VDD2
-------------- prepreg
--------------
GND
-------------- core
--------------
S5
We assume that pcb cores are hard enough to
achieve the required line impedances.
But, how about the impedances for the striplines
with one core and one prepreg layer as neighbours,
such as GND-S2-VDD1. Is there a rate of deviation after
pcb manufacturing due to prepreg shrinking? Is not it
more problematic if we have multiple core and
prepreg layers?
Any comments, suggestions? Thank you.
Cengiz Aydin
Researcher
Bilkent University
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